Patents by Inventor Takuya Tsurume

Takuya Tsurume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9954113
    Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: April 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Satoru Okamoto, Yutaka Okazaki, Yoshinobu Asami, Hiroaki Honda, Takuya Tsurume
  • Patent number: 9941115
    Abstract: A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like.
    Type: Grant
    Filed: July 25, 2013
    Date of Patent: April 10, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoko Tamura, Eiji Sugiyama, Yoshitaka Dozen, Koji Dairiki, Takuya Tsurume
  • Patent number: 9887232
    Abstract: To provide a photodetector circuit capable of obtaining signals in different periods without being affected by characteristics of a photoelectric conversion element. The photodetector circuit has n signal output circuits (n is a natural number of 2 or more) connected to the photoelectric conversion element. Further, the n signal output circuits each include the following: a transistor whose gate potential varies in accordance with the amount of light entering the photoelectric conversion element; a first switching element which holds the gate potential of the transistor; and a second switching element which controls a signal output from the transistor. Thus, after data based on the amount of light entering the photoelectric conversion elements is held as the gate potentials of the transistors, the second switching elements are turned on, whereby signals in different periods can be obtained without being affected by characteristics of the photoelectric conversion element.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventors: Yoshiyuki Kurokawa, Takuya Tsurume
  • Patent number: 9728631
    Abstract: An object of the present invention is to provide a semiconductor device having a conductive film, which sufficiently serves as an antenna, and a method for manufacturing thereof. The semiconductor device has an element formation layer including a transistor, which is provided over a substrate, an insulating film provided on the element formation layer, and a conductive film serving as an antenna, which is provided on the insulating film. The insulating film has a groove. The conductive film is provided along the surface of the insulating film and the groove. The groove of the insulating film may be provided to pass through the insulating film. Alternatively, a concave portion may be provided in the insulating film so as not to pass through the insulating film. A structure of the groove is not particularly limited, and for example, the groove can be provided to have a tapered shape, etc.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: August 8, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takuya Tsurume
  • Publication number: 20170084630
    Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.
    Type: Application
    Filed: September 2, 2016
    Publication date: March 23, 2017
    Inventors: Takuya TSURUME, Yoshitaka DOZEN
  • Patent number: 9559129
    Abstract: The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device including the antenna. The invention further provides a semiconductor device with high reliability that is formed by attaching an element formation layer and an antenna, wherein the element formation layer is not damaged due to a structure of the antenna. The semiconductor device includes the element formation layer provided over a substrate and the antenna provided over the element formation layer. The element formation layer and the antenna are electrically connected. The antenna has a base film and a conductive body, wherein at least a part of the conductive body is embedded in the base film. As a method for embedding the conductive body in the base film, a depression is formed in the base film and the conductive body is formed therein.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 31, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kyosuke Ito, Junya Maruyama, Takuya Tsurume, Shunpei Yamazaki
  • Patent number: 9536755
    Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: January 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryosuke Watanabe, Hidekazu Takahashi, Takuya Tsurume
  • Patent number: 9508619
    Abstract: A separation layer and a semiconductor element layer including a thin film transistor are formed. A conductive resin electrically connected to the semiconductor element layer is formed. A first sealing layer including a fiber and an organic resin layer is formed over the semiconductor element layer and the conductive resin. A groove is formed in the first sealing layer, the semiconductor element layer, and the separation layer. A liquid is dropped into the groove to separate the separation layer and the semiconductor element layer. The first sealing layer over the conductive resin is removed to form an opening. A set of the first sealing layer and the semiconductor element layer is divided into a chip. The chip is bonded to an antenna formed over a base material. A second sealing layer including a fiber and an organic resin layer is formed so as to cover the antenna and the chip.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: November 29, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoyuki Aoki, Takuya Tsurume, Hiroki Adachi, Nozomi Horikoshi, Hisashi Ohtani
  • Patent number: 9437620
    Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: September 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Yoshitaka Dozen
  • Publication number: 20160233340
    Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.
    Type: Application
    Filed: February 8, 2016
    Publication date: August 11, 2016
    Inventors: Akihisa SHIMOMURA, Satoru OKAMOTO, Yutaka OKAZAKI, Yoshinobu ASAMI, Hiroaki HONDA, Takuya TSURUME
  • Patent number: 9261554
    Abstract: To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: February 16, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takuya Tsurume, Etsuko Asano
  • Publication number: 20150255489
    Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.
    Type: Application
    Filed: May 21, 2015
    Publication date: September 10, 2015
    Inventors: Takuya TSURUME, Yoshitaka DOZEN
  • Publication number: 20150179696
    Abstract: To provide a photodetector circuit capable of obtaining signals in different periods without being affected by characteristics of a photoelectric conversion element. The photodetector circuit has n signal output circuits (n is a natural number of 2 or more) connected to the photoelectric conversion element. Further, the n signal output circuits each include the following: a transistor whose gate potential varies in accordance with the amount of light entering the photoelectric conversion element; a first switching element which holds the gate potential of the transistor; and a second switching element which controls a signal output from the transistor. Thus, after data based on the amount of light entering the photoelectric conversion elements is held as the gate potentials of the transistors, the second switching elements are turned on, whereby signals in different periods can be obtained without being affected by characteristics of the photoelectric conversion element.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Inventors: Yoshiyuki KUROKAWA, Takuya TSURUME
  • Patent number: 9059098
    Abstract: It is an object of the present invention to provide a semiconductor device where, even in a case of stacking a plurality of semiconductor elements provided over a substrate, the stacked semiconductor elements can be electrically connected through the substrate, and a manufacturing method thereof. According to one feature of the present invention, a method for manufacturing a semiconductor device includes the steps of selectively forming a depression in an upper surface of a substrate or forming an opening which penetrates the upper surface through a back surface; forming an element group having a transistor so as to cover the upper surface of the substrate and the depression, or the opening; and exposing the element group formed in the depression or the opening by thinning the substrate from the back surface.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: June 16, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Yoshitaka Dozen
  • Patent number: 9040998
    Abstract: A light-emitting device in which reduction in performance due to moisture is suppressed is provided. The light-emitting device has a structure in which a partition having a porous structure surrounds each of light-emitting elements. The partition having a porous structure physically adsorbs moisture; therefore, in the light-emitting device, the partition functions as a hygroscopic film at a portion extremely close to the light-emitting element, so that moisture or water vapor remaining in the light-emitting device or entering from the outside can be effectively adsorbed. Thus, reduction in performance of the light-emitting device due to moisture or water vapor can be effectively suppressed.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: May 26, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Hideomi Suzawa, Shunpei Yamazaki
  • Patent number: 9006635
    Abstract: To provide a photodetector circuit capable of obtaining signals in different periods without being affected by characteristics of a photoelectric conversion element. The photodetector circuit has n signal output circuits (n is a natural number of 2 or more) connected to the photoelectric conversion element. Further, the n signal output circuits each include the following: a transistor whose gate potential varies in accordance with the amount of light entering the photoelectric conversion element; a first switching element which holds the gate potential of the transistor; and a second switching element which controls a signal output from the transistor. Thus, after data based on the amount of light entering the photoelectric conversion elements is held as the gate potentials of the transistors, the second switching elements are turned on, whereby signals in different periods can be obtained without being affected by characteristics of the photoelectric conversion element.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takuya Tsurume
  • Patent number: 8956709
    Abstract: A first substrate including, on one of surfaces, a light absorption layer having metal nitride and a material layer which is formed so as to be in contact with the light absorption layer is provided; the surface of the first substrate on which the material layer is formed and a deposition target surface of a second substrate are disposed to face each other; and part of the material layer is deposited on the deposition target surface of the second substrate in such a manner that irradiation with laser light having a repetition rate of greater than or equal to 10 MHz and a pulse width of greater than or equal to 100 fs and less than or equal to 10 ns is performed from the other surface side of the first substrate to selectively heat part of the material layer which overlaps with the light absorption layer.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tomoya Aoyama, Takuya Tsurume, Takao Hamada
  • Patent number: 8951816
    Abstract: One embodiment of the present invention is a film forming method comprising: arranging a surface of a film formation substrate 10 including an absorption layer 12 on a first substrate 11 and a material layer 13 containing a film formation material and a surface of a film-formation target substrate 20 including a first layer 23 over a second substrate 22, so as to face each other; forming a second layer 13a containing the film formation material over the first layer 23 by performing first heat treatment on the material layer 13; and forming a third layer 13b containing the film formation material over the second layer 13a by performing second heat treatment on the material layer 13. In the second heat treatment, energy with a density higher than that in the first heat treatment is applied to the material layer.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: February 10, 2015
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Rena Tsuruoka, Hisao Ikeda, Takuya Tsurume, Tohru Sonoda, Satoshi Inoue
  • Publication number: 20140368230
    Abstract: To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.
    Type: Application
    Filed: August 28, 2014
    Publication date: December 18, 2014
    Inventors: Takuya TSURUME, Etsuko ASANO
  • Patent number: 8878223
    Abstract: A conductive layer serving as an auxiliary wiring is formed under a first electrode with a first insulating layer interposed therebetween, and the conductive layer and a second electrode are electrically connected to each other through an opening in the first insulating layer and the first electrode. A second insulating layer is formed over a sidewall of the opening so that the first electrode is not directly in contact with the second electrode in the opening. An EL layer is formed by evaporation in a state where a deposition target substrate is inclined to an evaporation source, so that the second insulating layer serves as an obstacle and a region where the EL layer is not formed by the evaporation and the conductive layer is exposed is formed in part of the opening in a self-aligned manner.
    Type: Grant
    Filed: April 4, 2012
    Date of Patent: November 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takuya Tsurume, Hisao Ikeda