Patents by Inventor Takuzo Ogawa

Takuzo Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060266981
    Abstract: The present invention provides an actuator element which functions stably in air and in vacuo, and can be driven at low voltages. The present invention provides an actuator element wherein at least two electrode layers 2, each of which is mutually insulated and comprises a gel composition comprising carbon nanotubes, an ionic liquid and a polymer, are formed on the surface of ion-conductive layer 1 comprising a gel composition comprising an ionic liquid and a polymer, so that the actuator element is capable of being flexed or deformed by creating a potential difference between the electrode layers; and an actuator element wherein at least two electrode layers 2, each of which is mutually insulated, are formed on the surface of ion-conductive layer 1, conductive layer 3 is formed on the surface of each electrode layer 2, and the actuator element is capable of being flexed or deformed by creating a potential difference between the conductive layers.
    Type: Application
    Filed: December 3, 2004
    Publication date: November 30, 2006
    Inventors: Kinji Asaka, Takanori Fukushima, Takuzo Ogawa, Atsuko Ogawa
  • Patent number: 4354121
    Abstract: A switching control circuit includes a first field controlled thyristor having a gate and a cathode between which a backward bias voltage source and a second field controlled thyristor are connected in series. Conduction of the second field controlled thyristor is controlled by controlling a voltage applied across the gate and the cathode, thereby to control conduction of the first field controlled thyristor. A large load current can be positively and safely turned on and off by a relatively small control current or voltage.
    Type: Grant
    Filed: July 10, 1981
    Date of Patent: October 12, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Terasawa, Kenji Miyata, Saburo Oikawa, Susumu Murakami, Masahiro Okamura, Takuzo Ogawa
  • Patent number: 4290830
    Abstract: A method of diffusing selectively aluminium into a single crystal silicon semiconductor substrate for fabricating a semiconductor device comprises the steps of forming a diffusion source layer of aluminium having a predetermined thickness on at least one of the major surfaces of the substrate in a predetermined pattern, forming an oxide film of a predetermined thickness through oxidation over the surface of the diffusion source layer and the exposed surface of the substrate, and heating the substrate inclusive of the exposed surface thereof and the diffusion source layer thereby to diffuse aluminium into the substrate. The thickness of the oxide film is so selected as to suppress vaporization of the aluminium and at the same time to be used as a diffusion mask without giving rise to crystallization into a cristobalite structure.
    Type: Grant
    Filed: October 16, 1979
    Date of Patent: September 22, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Mochizuki, Sadao Okano, Takuzo Ogawa
  • Patent number: 4262295
    Abstract: A semiconductor device for use as a surge arrester of NPN (or PNP) construction, in which two NPN (or PNP) elements having different avalanche breakdown voltages are so formed that at least the intermediate layers among three layers constituting such sections are continuously connected within the same semiconductive substrate.Carriers generated in the NPN (or PNP) element, which triggers avalanche at a low voltage, cause the NPN (or PNP) element having a higher avalanche breakdown voltage to be switched to a highly conductive state.The semiconductor device of the invention provides great surge capacity, and can be used as a surge arrester of increased reliability.
    Type: Grant
    Filed: January 30, 1979
    Date of Patent: April 14, 1981
    Assignee: Hitachi, Ltd.
    Inventors: Sadao Okano, Hiroaki Hachino, Takuzo Ogawa
  • Patent number: 4223328
    Abstract: A field controlled thyristor is disclosed which comprises a first emitter region exposed to one main surface of a semiconductor substrate and having a first conductivity type, a second emitter region exposed to the other main surface of the substrate and having a second conductivity type, a base region connecting the first and the second emitter region, and a gate region provided in the base region. The gate region consists of a slab-like first portion disposed parallel to both the emitter and a second portion connecting the first slab-like portion with one of the main surfaces of the semiconductor substrate. The impurity concentration of the base region is higher in the portion of the base region nearer to the emitter region having the same conductivity type as that of the base region than in the portion of the base region nearer to the emitter region having the opposite conductivity type to that of the base region.
    Type: Grant
    Filed: June 1, 1978
    Date of Patent: September 16, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Yoshio Terasawa, Kenji Miyata, Masayoshi Naito, Takuzo Ogawa, Masahiro Okamura
  • Patent number: 4219832
    Abstract: A thyristor comprising a four-layer semiconductor substrate of PNPN structure in which the sum of the thicknesses in the layered direction of the intermediate P-type and N-type layers is less than 400.mu., and the amount of impurities per unit area of either one of the outer P-type and N-type layers is less than 3.times.10.sup.14 atoms/cm.sup.2.
    Type: Grant
    Filed: August 20, 1976
    Date of Patent: August 26, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Naito, Takahiro Nagano, Takuzo Ogawa
  • Patent number: 4210464
    Abstract: The whole body of a semiconductor device with its pn junction exposed ends covered by insulating glass is subjected to the exposure to radiation having an energy of higher than 0.5 MeV in terms of the reduced energy of electron beams while the semiconductor device is maintained at temperatures higher than 300.degree. C., and preferably higher than 350.degree. C. As a result, the life time of the minority carriers in the semiconductor device can be shortened without increasing the leakage current in the reverse direction.
    Type: Grant
    Filed: January 31, 1978
    Date of Patent: July 1, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Tanaka, Masahiro Okamura, Toshikatsu Shirasawa, Takuzo Ogawa
  • Patent number: 4200877
    Abstract: Disclosed is a temperature-compensated voltage reference diode comprising a breakdown PN junction for establishing the zener breakdown voltage, a PN junction for temperature compensation having a temperature coefficient opposite to that of the breakdown PN junction, the breakdown PN junction and the temperature-compensating PN junction being integrally formed in a semiconductor substrate in a laminated fashion with these PN junctions connected in inverse series with each other, and a semiconductor region interposed between the breakdown PN junction and the temperature compensating PN junction for substantially preventing a transistor action from taking place between the respective PN junctions, wherein the semiconductor region is formed of at least one of a polycrystalline semiconductor layer and a single crystal semiconductor layer having an impurity concentration of higher than about 5.times.10.sup.18 atoms/cm.sup.3.
    Type: Grant
    Filed: December 13, 1977
    Date of Patent: April 29, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Takaya Suzuki, Mitsuru Ura, Takuzo Ogawa
  • Patent number: 4193826
    Abstract: A method of fabricating a semiconductor device through selective diffusion of aluminum vapor into a silicon substrate by heating a sealed tube in which the silicon substrate and an aluminum source are disposed. The diffusion is effected with a low concentration of aluminum smaller than about 10.sup.17 atoms/cm.sup.3, thereby making it possible to use a silicon oxide film as a diffusion mask for the selective diffusion of aluminum at predetermined region of the silicon substrate.
    Type: Grant
    Filed: August 7, 1978
    Date of Patent: March 18, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Yasuhiro Mochizuki, Hiroaki Hachino, Yasumichi Yasuda, Yutaka Misawa, Takuzo Ogawa
  • Patent number: 4164436
    Abstract: A semiconductor substrate having a single crystal semiconductor layer of one conductivity type exposed to the surface thereof is maintained at a temperature lower than the temperature at which the semiconductors is precipitated from the gas phase. In this state, a gas of a starting material of a semiconductor, a gas containing impurities capable of forming a semiconductor of the other conductivity type and a carrier gas therefore are fed onto the semiconductor substrate. Then, the semiconductor substrate is heated to form an amorphous or polycrystalline semiconductor layer of the other conductivity type on the semiconductor substrate.
    Type: Grant
    Filed: July 18, 1978
    Date of Patent: August 14, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuru Ura, Kenji Miyata, Takaya Suzuki, Takuzo Ogawa
  • Patent number: 4146906
    Abstract: A semiconductor device has one layer of a diode formed by diffusion of an impurity from a polycrystalline layer portion formed on a region in which the layer is to be formed. The polycrystalline layer portion is composed of two layers, the resistivity of the polycrystalline layer closer to the above-mentioned one layer of the diode being higher than that of the other polycrystalline layer.
    Type: Grant
    Filed: January 24, 1977
    Date of Patent: March 27, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Kenji Miyata, Mitsuru Ura, Takuzo Ogawa
  • Patent number: 4136351
    Abstract: A photo-coupled semiconductor device comprising a light-emitting semiconductor element, a light-receiving semiconductor element, and an insulation base supporting these two semiconductor elements. The insulation base has a pair of parallel surfaces and provides an optical path extending between the parallel surfaces for photo-coupling the semiconductor elements. Each of the semiconductor elements has at least two rigid electrodes extending in parallel to the parallel surfaces of the insulation base, and the electrodes are electrically and mechanically connected at one of their parallel surfaces by solder to conductive interconnection layers exposed at predetermined positions of one of the parallel surfaces of the insulation base. The device can satisfy both the desired increase in the efficiency of photo-coupling and the desired improvement in the massproductivity.
    Type: Grant
    Filed: April 28, 1977
    Date of Patent: January 23, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Yoshitaka Sugawara, Tatsuya Kamei, Susumu Murakami, Tadahiko Miyoshi, Takuzo Ogawa
  • Patent number: 4100310
    Abstract: In a method of doping impurities comprising mixing a carrier gas, a semiconductor compound gas and a doping gas and leading the mixed gas to a reaction chamber to form a semiconductor layer or a semiconductor oxide layer doped with impurities on a substrate inside the chamber, a part of the doping gas before mixing the doping gas with the other gases is taken and led to a gas analyzer and impurity concentration in the doping gas is monitored to control the impurity concentration in the doping gas.
    Type: Grant
    Filed: January 14, 1976
    Date of Patent: July 11, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuru Ura, Takuzo Ogawa, Takaya Suzuki, Yosuke Inoue, Masayoshi Nomura
  • Patent number: 4079405
    Abstract: A semiconductor photodetector comprising a first semiconductor layer having N-type conductivity; a second semiconductor layer having N-type conductivity, disposed in the vicinity of the first semiconductor layer and having a resistivity higher than that of the first semiconductor layer; a third region having P-type conductivity, disposed in the vicinity of the second semiconductor layer and having a thickness smaller than that of the second semiconductor layer; a first main electrode kept in ohmic contact with the first semiconductor layer; and a second main electrode kept in ohmic contact with a portion of the third region, the surface of the third region serving as a light receiving surface.
    Type: Grant
    Filed: June 24, 1975
    Date of Patent: March 14, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Hirobumi Ohuchi, Masahiro Okamura, Sumio Kawakami, Takuzo Ogawa
  • Patent number: 4058821
    Abstract: A photo-coupler semiconductor device includes a semiconductor light emitter and a semiconductor light detector coupled optically with each other through an optical guide. A portion of the optical guide close to the semiconductor light detector is made of glass. The glass portion of the optical guide is brought into intimate contact with a glass layer which is formed on a light sensitive region of the semiconductor light detector. The intimate contact is made by melting the glass portion on the glass layer.
    Type: Grant
    Filed: March 19, 1976
    Date of Patent: November 15, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Tadahiko Miyoshi, Yasutoshi Kurihara, Tatsuya Kamei, Takuzo Ogawa
  • Patent number: 4040084
    Abstract: A semiconductor device having a high blocking voltage, comprises a pair of principal surfaces opposite to each other, a circular groove cut in the peripheral portion of one of the principal surfaces and a PN junction formed along the surface of the groove and the one of the principal surfaces, wherein the region on the side of the PN junction near the one of the principal surfaces is of high impurity concentration, the outer edge of the PN junction appears in the bevel surface connecting the pair of principal surfaces, and the edge of the PN junction intersects the bevel surface in such a manner that the angle therebetween in the region of high impurity concentration is obtuse.
    Type: Grant
    Filed: September 5, 1975
    Date of Patent: August 2, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Tanaka, Masahiro Okamura, Takuzo Ogawa, Yutaka Misawa
  • Patent number: 4016593
    Abstract: A bidirectional photothyristor device comprises a semiconductive substrate including an NPNPN quintuple layer in which projections of both the outer layers Ns in the stacking direction are not overlapped so as to define two quadruple layer regions each having either one of the outer layers Ns as an end layer, a pair of main electrodes connecting the two quadruple layer regions in parallel relationship, a recess formed between the two quadruple layer regions within the semiconductive substrate and to which two intermediate P-N junctions are exposed, and means for applying a light trigger signal to the recess.
    Type: Grant
    Filed: June 3, 1975
    Date of Patent: April 5, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Nobutake Konishi, Tsutomu Yatsuo, Tatsuya Kamei, Masahiro Okamura, Takuzo Ogawa
  • Patent number: 3978514
    Abstract: A diode-integrated high speed thyristor formed into one body by using a separation region for preventing interference between a thyristor and a diode.
    Type: Grant
    Filed: February 13, 1974
    Date of Patent: August 31, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Takuzo Ogawa, Tsutomu Yatsuo, Keiichi Morita
  • Patent number: 3967308
    Abstract: A thyristor with a gate electrode formed on the side of an anode electrode. An auxiliary region of a large lateral resistance is formed in a surface layer of the substrate between the anode and gate electrodes.
    Type: Grant
    Filed: March 15, 1974
    Date of Patent: June 29, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Tsutomu Yatsuo, Tatsuya Kamei, Takuzo Ogawa, Tomoyuki Tanaka
  • Patent number: 3943547
    Abstract: A semiconductor device comprising a semiconductor substrate including at least three layers of alternating conductivity between a pair of principal surfaces, the side surface of said semiconductor substrate being formed in pulley-shape and the depth of the valley of the pulley-shape being selected from the most appropriate numerical range related with the dielectric constant of the surrounding medium and the thickness of the semiconductor substrate.
    Type: Grant
    Filed: December 3, 1973
    Date of Patent: March 9, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Takahiro Nagano, Tatsuya Kamei, Takuzo Ogawa