Patents by Inventor Tamotsu Ogata

Tamotsu Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200212057
    Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.
    Type: Application
    Filed: March 9, 2020
    Publication date: July 2, 2020
    Inventor: Tamotsu OGATA
  • Publication number: 20200098775
    Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventor: Tamotsu OGATA
  • Patent number: 10593687
    Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 17, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10559581
    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: February 11, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Yamashita, Tamotsu Ogata, Masamichi Fujito, Tomoya Saito
  • Patent number: 10522558
    Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: December 31, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10446569
    Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tamotsu Ogata
  • Patent number: 10438961
    Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: October 8, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10424591
    Abstract: In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the position of the upper surface of the element isolation insulating film is set to be lower than the position of the main surface of a semiconductor substrate. A buried silicon nitride film and an etching stopper film are formed over the element isolation insulating film. The position of the upper surface of the etching stopper film is higher than that of the upper surface of the element isolation insulating film defining a peripheral active region.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: September 24, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Publication number: 20190273057
    Abstract: To provide a semiconductor device that prevents a surface of a bonding pad from being made rough and can also reduce dimensions of the bonding pad, a semiconductor device according to an embodiment includes a bonding pad containing aluminum, a titanium nitride film, a passivation film, and a sidewall protection film including a first layer and a second layer. An opening is provided in the titanium nitride film and the passivation film. The opening includes a sidewall and exposes the bonding pad therethrough. The first layer of the sidewall protection film covers at least the titanium nitride film over the sidewall, and the second layer covers the first layer. A material forming the first layer and a material forming the second layer are different from each other in an etching rate in etching under the same condition.
    Type: Application
    Filed: February 19, 2019
    Publication date: September 5, 2019
    Inventor: Tamotsu OGATA
  • Publication number: 20190172835
    Abstract: A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a laminated film of a silicon oxide film and a silicon nitride film, and the silicon oxide film is particularly formed to directly contact the sidewall of a memory gate electrode and the side end portion of a charge storage film; on the other hand, an offset spacer formed in a MISFET is formed by a silicon nitride film. Particularly in the MISFET, the silicon nitride film directly contacts both the sidewall of a gate electrode and the side end portion of a high dielectric constant film.
    Type: Application
    Filed: January 31, 2019
    Publication date: June 6, 2019
    Inventor: Tamotsu OGATA
  • Publication number: 20190172837
    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.
    Type: Application
    Filed: February 7, 2019
    Publication date: June 6, 2019
    Inventors: Tomohiro YAMASHITA, Tamotsu OGATA, Masamichi FUJITO, Tomoya SAITO
  • Patent number: 10249638
    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: April 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Yamashita, Tamotsu Ogata, Masamichi Fujito, Tomoya Saito
  • Publication number: 20190096902
    Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 28, 2019
    Inventor: Tamotsu OGATA
  • Publication number: 20190088670
    Abstract: In a memory cell region of a semiconductor device, a memory active region is defined by an element isolation insulating film. In the memory cell region, the position of the upper surface of the element isolation insulating film is set to be lower than the position of the main surface of a semiconductor substrate. A buried silicon nitride film and an etching stopper film are formed over the element isolation insulating film. The position of the upper surface of the etching stopper film is higher than that of the upper surface of the element isolation insulating film defining a peripheral active region.
    Type: Application
    Filed: July 11, 2018
    Publication date: March 21, 2019
    Inventor: Tamotsu OGATA
  • Patent number: 10204789
    Abstract: Over a semiconductor substrate, a memory gate electrode for a nonvolatile memory cell is formed via a first insulating film having an internal charge storage portion. A dummy control gate electrode is formed so as to be adjacent to the memory gate electrode via a second insulating film. The memory and the dummy control gate electrodes are made of different materials. A third insulating film is formed so as to cover the memory and the dummy control gate electrodes and then polished to expose the memory and the dummy control gate electrodes. Then, etching is performed under a condition in which the memory gate electrode is less likely to be etched than the dummy control gate electrode to remove the dummy control gate electrode. Then, in a trench as a region from which the dummy control gate electrode is removed, a control gate electrode for the memory cell is formed.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tamotsu Ogata, Tatsuyoshi Mihara
  • Patent number: 10192879
    Abstract: An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A memory cell of the nonvolatile memory includes a control gate electrode formed over a semiconductor substrate via a first insulating film and a memory gate electrode formed over the semiconductor substrate via a second insulating film to be adjacent to the control gate electrode via the second insulating film. The second insulating film includes a third insulating film made of a silicon dioxide film, a fourth insulating film made of a silicon nitride film over the third insulating film, and a fifth insulating film over the fourth insulating film. The fifth insulating film includes a silicon oxynitride film. Between the memory gate electrode and the semiconductor substrate, respective end portions of the fourth and fifth insulating films are located closer to a side surface of the memory gate electrode than an end portion of a lower surface of the memory gate electrode.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: January 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Tamotsu Ogata
  • Patent number: 10153293
    Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tamotsu Ogata
  • Publication number: 20180315768
    Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.
    Type: Application
    Filed: February 24, 2018
    Publication date: November 1, 2018
    Inventors: Tomohiro YAMASHITA, Tamotsu OGATA, Masamichi FUJITO, Tomoya SAITO
  • Patent number: 10090399
    Abstract: The reliability of a semiconductor device having a nonvolatile memory is improved. The memory cell of the nonvolatile memory is of a split gate type, and has first and second n type semiconductor regions in a semiconductor substrate, a control electrode formed over the substrate between the semiconductor regions via a first insulation film, and a memory gate electrode formed over the substrate between the semiconductor regions via a second insulation film having a charge accumulation part. The SSI method is used for write to the memory cell. During the read operation of the memory cell, the first and second semiconductor regions function as source and drain regions, respectively. The first width of the first sidewall spacer formed adjacent to the side surface of the memory gate electrode is larger than the second width of the second sidewall spacer formed adjacent to the side surface of the control gate electrode.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 2, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hirofumi Tokita, Tamotsu Ogata
  • Publication number: 20180090508
    Abstract: A semiconductor device having a nonvolatile memory cell arranged in a p-type well (active region) PW1 in a memory cell region 1A in a semiconductor substrate 1 and an MISFET arranged in a p-type well PW2 (active region) or an n-type well (active region) in a peripheral circuit region 2A is constructed as follows. The surface of an element isolation region STI1 surrounding the p-type well PW1 is set lower than the surface of an element isolation region STI2 surrounding the p-type well PW2 or the n-type well (H1<H2). By making the surface of the element isolation region STI1 receded and lowered, the effective channel width of both a control transistor and a memory transistor can be increased. Since the surface of the element isolation region STI2 is not made receded, an undesired film can be prevented from being residual over a dummy gate electrode.
    Type: Application
    Filed: July 25, 2017
    Publication date: March 29, 2018
    Inventor: Tamotsu OGATA