Patents by Inventor Tanuj TRIVEDI

Tanuj TRIVEDI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088253
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
  • Patent number: 11862703
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
  • Publication number: 20230420501
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
  • Patent number: 11791380
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Rahul Ramaswamy, Walid M. Hafez, Tanuj Trivedi, Jeong Dong Kim, Ting Chang, Babak Fallahazad, Hsu-Yu Chang, Nidhi Nidhi
  • Patent number: 11581404
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Tanuj Trivedi, Jeong Dong Kim, Walid M. Hafez, Hsu-Yu Chang, Rahul Ramaswamy, Ting Chang, Babak Fallahazad
  • Publication number: 20220359697
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Application
    Filed: July 21, 2022
    Publication date: November 10, 2022
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
  • Patent number: 11437483
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 6, 2022
    Assignee: Intel Corporation
    Inventors: Tanuj Trivedi, Rahul Ramaswamy, Jeong Dong Kim, Babak Fallahazad, Hsu-Yu Chang, Ting Chang, Nidhi Nidhi, Walid M. Hafez
  • Publication number: 20220093588
    Abstract: Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, and methods of fabricating adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. One or more gate stacks is over the first and second vertical arrangements of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between adjacent ones of the first epitaxial source or drain structures and between adjacent ones of the second epitaxial source or drain structures.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Inventors: Sairam SUBRAMANIAN, Walid M. HAFEZ, Hsu-Yu CHANG, Chia-Hong JAN, Tanuj TRIVEDI
  • Publication number: 20210399002
    Abstract: Embodiments disclosed herein include a semiconductor device and methods of forming such a device. In an embodiment, the semiconductor device comprises a substrate and a transistor on the substrate. In an embodiment, the transistor comprises a first gate electrode, where the first gate electrode is part of a first array of gate electrodes with a first pitch. In an embodiment, the first gate electrode has a first average grain size. In an embodiment, the semiconductor device further comprises a component cell on the substrate. In an embodiment, the component cell comprises a second gate electrode, where the second gate electrode is part of a second array of gate electrodes with a second pitch that is larger than the first pitch. In an embodiment, the second gate electrode has a second average grain size that is larger than the first average grain size.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 23, 2021
    Inventors: Tanuj TRIVEDI, Walid M. HAFEZ, Rohan BAMBERY, Daniel B. O'Brien, Christopher Alan NOLPH, Rahul RAMASWAMY, Ting CHANG
  • Publication number: 20210280683
    Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 9, 2021
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Babak FALLAHAZAD, Hsu-Yu CHANG, Ting CHANG, Nidhi NIDHI, Walid M. HAFEZ
  • Publication number: 20210257452
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.
    Type: Application
    Filed: February 19, 2020
    Publication date: August 19, 2021
    Inventors: Tanuj TRIVEDI, Jeong Dong KIM, Walid M. HAFEZ, Hsu-Yu CHANG, Rahul RAMASWAMY, Ting CHANG, Babak FALLAHAZAD
  • Publication number: 20210257453
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Inventors: Tanuj TRIVEDI, Jeong Dong KIM, Walid M. HAFEZ, Hsu-Yu CHANG, Rahul RAMASWAMY, Ting CHANG, Babak FALLAHAZAD
  • Patent number: 11094782
    Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Tanuj Trivedi, Jeong Dong Kim, Walid M. Hafez, Hsu-Yu Chang, Rahul Ramaswamy, Ting Chang, Babak Fallahazad
  • Publication number: 20210193844
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a source, a drain, and a semiconductor channel between the source and the drain. In an embodiment, the semiconductor channel has a non-uniform strain through a thickness of the semiconductor channel. In an embodiment, the semiconductor device further comprises a gate stack around the semiconductor channel.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Inventors: Rahul RAMASWAMY, Hsu-Yu CHANG, Babak FALLAHAZAD, Hsiao-Yuan WANG, Ting CHANG, Tanuj TRIVEDI, Jeong Dong KIM, Nidhi NIDHI, Walid M. HAFEZ
  • Publication number: 20210184001
    Abstract: Embodiments disclosed herein include nanowire and nanoribbon devices with non-uniform dielectric thicknesses. In an embodiment, the semiconductor device comprises a substrate and a plurality of first semiconductor layers in a vertical stack over the substrate. The first semiconductor layers may have a first spacing. In an embodiment, a first dielectric surrounds each of the first semiconductor layers, and the first dielectric has a first thickness. The semiconductor device may further comprise a plurality of second semiconductor layers in a vertical stack over the substrate, where the second semiconductor layers have a second spacing that is greater than the first spacing. In an embodiment a second dielectric surrounds each of the second semiconductor layers, and the second dielectric has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Ting CHANG, Walid M. HAFEZ, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
  • Publication number: 20210184032
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Walid M. HAFEZ, Hsu-Yu CHANG, Ting CHANG, Babak FALLAHAZAD, Tanuj TRIVEDI, Jeong Dong KIM
  • Publication number: 20210184045
    Abstract: Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Nidhi NIDHI, Ting CHANG, Hsu-Yu CHANG, Tanuj TRIVEDI, Jeong Dong KIM, Babak FALLAHAZAD
  • Publication number: 20210183850
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a source. The source has a first conductivity type and a first insulator separates the source from the semiconductor substrate. The semiconductor device further comprises a drain. The drain has a second conductivity type that is opposite from the first conductivity type, and a second insulator separates the drain from the semiconductor substrate. In an embodiment, the semiconductor further comprises a semiconductor body between the source and the drain, where the semiconductor body is spaced away from the semiconductor substrate.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Walid M. HAFEZ, Hsu-Yu CHANG, Ting CHANG, Babak FALLAHAZAD, Tanuj TRIVEDI, Jeong Dong KIM, Ayan KAR, Benjamin ORR
  • Publication number: 20210184051
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, a first transistor over the substrate, where the first transistor comprises a vertical stack of first semiconductor channels, and a first gate dielectric surrounding each of the first semiconductor channels. The first gate dielectric has a first thickness. In an embodiment, the semiconductor device further comprises a second transistor over the substrate, where the second transistor comprises a second semiconductor channel. The second semiconductor channel comprises pair of sidewalls and a top surface. In an embodiment, a second gate dielectric is over the pair of sidewalls and the top surface of the fin, where the second gate dielectric has a second thickness that is greater than the first thickness.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Tanuj TRIVEDI, Rahul RAMASWAMY, Jeong Dong KIM, Ting CHANG, Walid M. HAFEZ, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI
  • Publication number: 20210184000
    Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: Rahul RAMASWAMY, Walid M. HAFEZ, Tanuj TRIVEDI, Jeong Dong KIM, Ting CHANG, Babak FALLAHAZAD, Hsu-Yu CHANG, Nidhi NIDHI