Patents by Inventor Tapan J. Chakraborty
Tapan J. Chakraborty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9285418Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.Type: GrantFiled: March 11, 2013Date of Patent: March 15, 2016Assignee: QUALCOMM IncorporatedInventors: Tapan J Chakraborty, Rajamani Sethuram, Ratibor Radojcic
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Publication number: 20130285687Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.Type: ApplicationFiled: March 11, 2013Publication date: October 31, 2013Applicant: QUALCOMM INCORPORATEDInventors: Tapan J. Chakraborty, Rajamani Sethuram, Riko Radojcic
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Patent number: 7962885Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.Type: GrantFiled: December 4, 2007Date of Patent: June 14, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Patent number: 7958479Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.Type: GrantFiled: December 4, 2007Date of Patent: June 7, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Patent number: 7949915Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.Type: GrantFiled: December 4, 2007Date of Patent: May 24, 2011Assignee: Alcatel-Lucent USA Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Publication number: 20090144593Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports parallel access to one or more system-on-chip devices, including methods for describing and using parallel access for testing.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Treuren
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Publication number: 20090144594Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Publication number: 20090144592Abstract: The present invention provides a new hardware description language for chip-level JTAG testing. This new hardware description language, referred to as New BSDL (NSDL), enables testing resources of a system-on-chip to be described, thereby enabling the system-on-chip to be described in a manner that facilitates testing of the system-on-chip. The present invention provides a bottom-up approach to describing a system-on-chip. The present invention supports algorithmic descriptions of each of the components of the system-on-chip, and supports an algorithmic description of interconnections between the components of the system-on-chip, thereby enabling generation of an algorithmic description of the entire system-on-chip or portions of the system-on-chip. The present invention supports devices adapted for dynamically modifying the scan path of a system-on-chip (referred to herein as crossroad devices), including methods for describing such devices and use of such devices to perform testing of system-on-chips.Type: ApplicationFiled: December 4, 2007Publication date: June 4, 2009Inventors: Tapan J. Chakraborty, Chen-Huan Chiang, Suresh Goyal, Michele Portolan, Bradford Gene Van Treuren
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Patent number: 7284159Abstract: A method and system are disclosed for fault injection using Boundary Scan resources compliant with 1149.1, while operating in system mode. The system has two register circuits, one, for storing and updating fault selection data and another, for storing and updating fault injection values.Type: GrantFiled: August 26, 2003Date of Patent: October 16, 2007Assignee: Lucent Technologies Inc.Inventors: Tapan J. Chakraborty, Chen-Huan Chiang
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Patent number: 5606567Abstract: High speed testing of a digital circuit may be performed although the rated frequency of the circuit exceeds the frequency capability of the test equipment. A digital circuit may be designed such that a controllable delay may be introduced in the timing paths of the circuit during testing using test stimuli which are applied at a clock rate that is less than the rated frequency of the circuit. By adding delay to the combinational signal path, testing of the circuit for operation at the maximum operating frequency is achieved during testing at a clock rate which is within the capability of the test equipment. The controllable delay may be incorporated as a delay element into a single-clock circuit and controlled by manipulation of the duty-cycle of a clock waveform which is applied to the circuit. The delay circuit is so designed that its function is also testable. In a multi-clock circuit, the delay is added to the circuit by skewing one clock signal with respect to the other clock signals.Type: GrantFiled: October 21, 1994Date of Patent: February 25, 1997Assignee: Lucent Technologies Inc.Inventors: Vishwani D. Agrawal, Tapan J. Chakraborty
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Patent number: 5499249Abstract: Testing of a sequential circuit (10) containing at least one embedded RAM (16) is accomplished by first generating a set of sequential vectors and then applying the vectors in sequence to a set of primary circuit inputs (PO.sub.o -PO.sub.j). The vectors are generated such that upon application to the circuit, the vectors excite potential faults at nodes (A) upstream of the RAM and propagate the effects of the faults through the RAM to the primary circuit outputs (PO.sub.o -PO.sub.j). Also, the test vectors serve to excite faults downstream of the RAM by propagating values through the RAM needed to excite the downstream faults. The fault effects (if any) that propagate to the circuit primary outputs are compared to a set of reference values to determine if any faults are present.Type: GrantFiled: May 31, 1994Date of Patent: March 12, 1996Assignee: AT&T Corp.Inventors: Vishwani D. Agrawal, Tapan J. Chakraborty
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Patent number: 5365528Abstract: To detect a delay fault along a signal path of interest (12) in a sequential digital circuit (10), a source flip-flop (14) and a destination flip-flop (16), proximate the beginning and end of the path, respectively, are designated in the circuit. Next, the signal path is activated to establish what logic values are necessary at the input of each of a set of combinational elements (18.sub.1 -18.sub.p) in the path to propagate a selected signal transition from the source flip-flop to the destination flip-flop. A first and second backward justification process is carried out to synthesize a first sequence to propagate a selected logic value from a primary circuit input to the source flip-flop to cause it to generate the selected signal transition to propagate to the destination flip-flop. A second backward justification process is carried out to synthesize a second vector sequence which serves to propagate the value latched in the destination flip-flop to a primary output.Type: GrantFiled: April 3, 1992Date of Patent: November 15, 1994Assignee: AT&T Bell LaboratoriesInventors: Vishwani D. Agrawal, Tapan J. Chakraborty