Patents by Inventor Tarun Batra

Tarun Batra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10332290
    Abstract: Technology related to efficient, coverage-optimized, resolution-independent, and anti-aliased graphics processing is described. Uniquely, an example system may include a graphics processing unit configured to receive a plurality of vertices representing a control polygon of a curve and expanding the control polygon of the curve. The graphic processing unit may further tessellate the control polygon into a plurality of tiles, select a subset of tiles from the plurality of tiles based on satisfying selection criteria, rasterize fragments using the selected subset of tiles, and render the curve based on the fragments.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: June 25, 2019
    Assignee: Adobe Inc.
    Inventors: Tarun Beri, Vineet Batra
  • Patent number: 7735030
    Abstract: A method of simulating a restorable register in a power domain of an RTL (register transfer level) design includes: specifying the power domain in the RTL design, wherein the power domain includes one or more registers and is configured to change power levels separately from other portions of the RTL design; identifying the restorable register in the power domain, wherein the restorable register is updated during power-on operations in the power domain; simulating the restorable register in a power cycle; and saving one or more values from the simulated restorable register. Simulating the restorable register includes: maintaining one or more backup values during a power-off operation for updating the restorable register after the power-off operation; and updating the restorable register during a power-on operation after the power-off operation by using the one or more backup values.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: June 8, 2010
    Assignee: Cadence Design Systems, Inc.
    Inventors: Nadeem Kalil, Philip Giangarra, Ritesh Goel, Tarun Batra