Abstract: Disclosed herein are approaches for modifying patterned features using a directional etch. In one approach, a method may include providing a stack of layers of a semiconductor device, forming an opening through the stack of layers, the opening defined by a first sidewall and a second sidewall, and delivering ions into the first sidewall in a reactive ion etching process. The ions maybe delivered at a first non-zero angle relative to a perpendicular extending from the substrate, wherein the reactive ion etching process removes a first portion of the stack of layers from just a lower section of the first sidewall.

Abstract: Disclosed herein are approaches for device modification, namely, trench elongation. In one approach, a method may include providing a substrate including a plurality of surface features defining a plurality of trenches, wherein a first trench has a first trench length extending in a first direction, wherein a second trench connected to the first trench has a second trench length extending in a second direction, and wherein the first direction and the second direction are non-parallel. The method may further include delivering ions into the substrate in a reactive ion etching process, wherein the ions are delivered at a non-zero angle relative to a perpendicular extending from the substrate, and wherein the reactive ion etching process increases the first trench length of the first trench without increasing the second trench length of the second trench.

Abstract: Disclosed herein are approaches for modifying patterned features using a directional etch. In one approach, a method may include providing a stack of layers of a semiconductor device, forming an opening through the stack of layers, the opening defined by a first sidewall and a second sidewall, and delivering ions into the first sidewall in a reactive ion etching process. The ions maybe delivered at a first non-zero angle relative to a perpendicular extending from the substrate, wherein the reactive ion etching process removes a first portion of the stack of layers from just a lower section of the first sidewall.

Abstract: Disclosed herein are approaches for device modification, namely, trench elongation. In one approach, a method may include providing a substrate including a plurality of surface features defining a plurality of trenches, wherein a first trench has a first trench length extending in a first direction, wherein a second trench connected to the first trench has a second trench length extending in a second direction, and wherein the first direction and the second direction are non-parallel. The method may further include delivering ions into the substrate in a reactive ion etching process, wherein the ions are delivered at a non-zero angle relative to a perpendicular extending from the substrate, and wherein the reactive ion etching process increases the first trench length of the first trench without increasing the second trench length of the second trench.

Abstract: Methods of processing a feature on a semiconductor workpiece are disclosed. The method is performed after features have been created on the workpiece. An etching species may be directed toward the workpiece at a non-zero tilt angle. In certain embodiments, the tilt angle may be 30° or more. Further, the etching species may also be directed with a non-zero twist angle. In certain embodiments, the etching species may sputter material from the features, while in other embodiments, the etching species may be a chemically reactive species. By adjusting the tilt and twist angles, as well as the flow rate of the etching species and the exposure time, the LER and LWR of a feature may be reduced with minimal impact of the CD of the feature.

Abstract: Methods of processing a feature on a semiconductor workpiece are disclosed. The method is performed after features have been created on the workpiece. An etching species may be directed toward the workpiece at a non-zero tilt angle. In certain embodiments, the tilt angle may be 30° or more. Further, the etching species may also be directed with a non-zero twist angle. In certain embodiments, the etching species may sputter material from the features, while in other embodiments, the etching species may be a chemically reactive species. By adjusting the tilt and twist angles, as well as the flow rate of the etching species and the exposure time, the LER and LWR of a feature may be reduced with minimal impact of the CD of the feature.

Abstract: A composition comprising: (A) an organopolysiloxane, (B) a filler and (C) a filler treatment agent, comprising a mixture of two organopolysiloxanes having the general formulas (I) and (II), R1R2R3Si—[(CH2)n1(Me2SiO)m1]r—[O-(Me2SiO)m3]p-(Me2Si)o(CH2)n2(Me2SiO)m2—(CH2)n3—Si(OR43)3 (I), wherein ‘Me’ is methyl group, R1, R2 and R3 are independently selected from an alkyl group having 1 to 20 carbon atoms, an alkenyl group having 2 to 4 carbon atoms, an alkoxy group having 1 to 3 carbon atoms or —(OSiR7R8R9), in which R7, R8 and R9 are independently selected from an alkyl group having 1 to 4 carbon atoms, R4 is an alkyl group having 1 to 4 carbon atoms, n1, n2, m1, m3 and o are integers from 1 to 200, m2, n3, r and p are integers from 0 to 200, r and p are not 0 at the same time, (R5O)3Si—[(CH2)n1(Me2SiO)m1]r—(CH2)n4—[O-(Me2SiO)m3]p-(Me2Si)o-(CH2)n2-(Me02SiO)m2—(CH2)n3—Si(OR6)3 (II), wherein R5 and R6 are an alkyl group having 1 to 4 carbon atoms, n1, m1, m3, o and n2 are integers from 1 to 200, n3, n4, m2, r and

Abstract: The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.

Abstract: The present disclosure is directed to structures and processing for three-dimensional transistor devices. In some approaches, a method may include providing a plurality of fin structures formed from a substrate, the plurality of fin structures disposed subjacent to a hard mask layer, and directing angled ions at the plurality of fin structures. The angled ions may form a non-zero angle of incidence with respect to a perpendicular to a plane of the substrate, wherein the angled ions etch the plurality of fin structures to form a stack of isolated nanowires within the plurality of fin structures. The method may further include removing the hard mask layer, and forming a stopping layer over the stack of isolated nanowires.

Abstract: A composition comprising: (A) an organopolysiloxane, (B) a filler and (C) a filler treatment agent, comprising a mixture of two organopolysiloxanes having the general formulas (I) and (II), R1R2R3Si—[ (CH2)m1 (Me2SiO)m1]r—[O-(Me2SiO)m3]p-(Me2Si)0 (CH2)m2 (Me2SiO)m2—(CH2)m3—Si (OR43)3 (I), wherein ‘Me’ is methyl group, R1, R2 and R3 are independently selected from an alkyl group having 1 to 20 carbon atoms, an alkenyl group having 2 to 4 carbon atoms, an alkoxy group having 1 to 3 carbon atoms or (OSiR7R8R9), in which R7, R8 and R9 are independently selected from an alkyl group having 1 to 4 carbon atoms, R4 is an alkyl group having 1 to 4 carbon atoms, n1, n2, m1, m3 and o are integers from 1 to 200, m2, n3, r and p are integers from 0 to 200, r and p are not 0 at the same time, (R5O)3Si—[(CH2)n1(Me2SiO)m1]r—(CH2)n4—[O-(Me2SiO)m3]p-(Me2Si)o-(CH2)m2— (Me2SiO)m2—(CH2)n3—Si(OR6)3 (II), wherein R5 and R6 are an alkyl group having 1 to 4 carbon atoms, n1, m1, m3, o and n2 are integers from 1 to 200, n3, n4, m2, r