Patents by Inventor Tathagata Chatterjee

Tathagata Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8026507
    Abstract: A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 27, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Tathagata Chatterjee, Henry Litzmann Edwards, Chris Bowen
  • Publication number: 20110127572
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Application
    Filed: February 9, 2011
    Publication date: June 2, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Patent number: 7943450
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: May 17, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Patent number: 7910918
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: March 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Patent number: 7859289
    Abstract: A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: December 28, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Tathagata Chatterjee, Amitava Chatterjee
  • Publication number: 20100274506
    Abstract: A method for measuring interface traps in a MOSFET, includes measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.
    Type: Application
    Filed: July 6, 2010
    Publication date: October 28, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata Chatterjee, Amitava Chatterjee
  • Patent number: 7704813
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: April 27, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Publication number: 20100093140
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Application
    Filed: August 17, 2009
    Publication date: April 15, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Patent number: 7692217
    Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: April 6, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang, Lance Stanford Robertson
  • Patent number: 7687856
    Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: March 30, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Xiaoju Wu
  • Patent number: 7683364
    Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.
    Type: Grant
    Filed: September 4, 2008
    Date of Patent: March 23, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Chris Bowen, Tathagata Chatterjee
  • Publication number: 20100065823
    Abstract: A gated resonant tunneling diode (GRTD) that operates without cryogenic cooling is provided. This GRTD employs conventional CMOS process technology, preferably at the 65 nm node and smaller, which is different from other conventional quantum transistors that require other, completely different process technologies and operating conditions. To accomplish this, the GRTD uses a body of a first conduction type with a first electrode region and a second electrode region (each of a second conduction type) formed in the body. A channel is located between the first and second electrode regions in the body. A barrier region of the first conduction type is formed in the channel (with the doping level of the barrier region being greater than the doping level of the body), and a quantum well region of the second conduction type formed in the channel. Additionally, the barrier region is located between each of the first and second electrode regions and the quantum well region.
    Type: Application
    Filed: August 17, 2009
    Publication date: March 18, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Robert C. Bowen, Tathagata Chatterjee
  • Publication number: 20100045365
    Abstract: A gated quantum well device formed as an MOS capacitor is disclosed. The quantum well is an inversion region less than 20 nanometers wide under the MOS gate. The device may be fabricated in either polarity, and integrated into a CMOS IC, configured as a quantum dot device or a quantum wire device. The device may be operated as a precision charge pump, with a minority carrier injection region added to speed well filling.
    Type: Application
    Filed: August 20, 2009
    Publication date: February 25, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata CHATTERJEE, Henry Litzmann EDWARDS, Chris BOWEN
  • Patent number: 7638415
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: December 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
  • Patent number: 7615805
    Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: November 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, Tathagata Chatterjee, Lily X. Springer, Jeffrey P. Smith
  • Patent number: 7595649
    Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: September 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Tathagata Chatterjee, Joe R. Trogolo, Kaiyuan Chen, Henry Litzmann Edwards
  • Publication number: 20090159967
    Abstract: One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.
    Type: Application
    Filed: December 19, 2007
    Publication date: June 25, 2009
    Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Gabriel J. Gomez
  • Publication number: 20090140346
    Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.
    Type: Application
    Filed: November 30, 2007
    Publication date: June 4, 2009
    Inventors: Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang, Lance Stanford Robertson
  • Publication number: 20090079446
    Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata Chatterjee, Joe R. Trogolo, Kaiyuan Chen, Henry Litzmann Edwards
  • Publication number: 20090057651
    Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.
    Type: Application
    Filed: September 4, 2008
    Publication date: March 5, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Chris Bowen, Tathagata Chatterjee