Patents by Inventor Tathagata Chatterjee
Tathagata Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7615805Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.Type: GrantFiled: May 8, 2007Date of Patent: November 10, 2009Assignee: Texas Instruments IncorporatedInventors: Joe R. Trogolo, Tathagata Chatterjee, Lily X. Springer, Jeffrey P. Smith
-
Patent number: 7595649Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.Type: GrantFiled: September 25, 2007Date of Patent: September 29, 2009Assignee: Texas Instruments IncorporatedInventors: Tathagata Chatterjee, Joe R. Trogolo, Kaiyuan Chen, Henry Litzmann Edwards
-
Publication number: 20090159967Abstract: One embodiment of the invention relates to a semiconductor device formed over a semiconductor body. In this device, source and drain regions are formed in the body about lateral edges of a gate electrode and are separated from one another by a gate length. A channel region, which is configured to allow charged carriers to selectively flow between the source and drain regions during operation of the device, has differing widths under the gate electrode. These widths are generally perpendicular to the gate length. Other devices, methods, and systems are also disclosed.Type: ApplicationFiled: December 19, 2007Publication date: June 25, 2009Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Gabriel J. Gomez
-
Publication number: 20090140346Abstract: One embodiment of the invention relates to an integrated circuit. The integrated circuit includes a first matched transistor comprising: a first source region, a first drain region formed within a first drain well extension, and a first gate electrode having lateral edges about which the first source region and first drain region are laterally disposed. The integrated circuit also includes a second matched transistor comprising: a second source region, a second drain region formed within a second drain well extension, and a second gate electrode having lateral edges about which the second source region and second drain region are laterally disposed. Analog circuitry is associated with the first and second matched transistors, which analog circuitry utilizes a matching characteristic of the first and second matched transistors to facilitate analog functionality. Other devices, methods, and systems are also disclosed.Type: ApplicationFiled: November 30, 2007Publication date: June 4, 2009Inventors: Henry Litzmann Edwards, Hisashi Shichijo, Tathagata Chatterjee, Shyh-Horng Yang, Lance Stanford Robertson
-
Publication number: 20090079446Abstract: Measurements of parameters of MOS transistors, also known as MOSFETs, such as threshold potentials, require accurate estimates of source and drain series resistance. In cases where connections to the MOSFET include significant external series resistance, as occurs in probing transistors that are partially fabricated or deprocessed, accurate estimates of external resistances are also required. This invention comprises a method for estimating series resistances of MOSFETs, including resistances associated with connections to the MOSFET, such as probe contacts. This method is applicable to any MOSFET which can be accessed on source, drain, gate and substrate terminals, and does not require other test structures or special connections, such as Kelvin connections.Type: ApplicationFiled: September 25, 2007Publication date: March 26, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Tathagata Chatterjee, Joe R. Trogolo, Kaiyuan Chen, Henry Litzmann Edwards
-
Publication number: 20090056345Abstract: A nanoscale thermoelectric device, which may be operated as a refrigerator or as a thermoelectric generator includes N-type and p-type active areas connected to a central terminal and end electrodes made of interconnect metal. Reducing lateral dimensions of the active areas reduces vertical thermal conduction, thus improving the efficiency of the thermoelectric device. The thermoelectric device may be integrated into the fabrication process sequence of an IC without adding process cost or complexity. Operated as a refrigerator, the central terminal may be configured to cool a selected component in the IC, such as a transistor. Operated as a thermoelectric generator with a heat source applied to the central terminal, the end terminals may provide power to a circuit in the IC.Type: ApplicationFiled: August 29, 2008Publication date: March 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: HENRY LITZMANN EDWARDS, TATHAGATA CHATTERJEE
-
Publication number: 20090061606Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.Type: ApplicationFiled: November 7, 2008Publication date: March 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: MARTIN MOLLAT, TATHAGATA CHATTERJEE, HENRY L. EDWARDS, LANCE S. ROBERTSON, RICHARD B. IRWIN, BINGHUA HU
-
Publication number: 20090057651Abstract: A gated resonant tunneling diode (GRTD) is disclosed including a metal oxide semiconductor (MOS) gate over a gate dielectric layer which is biased to form an inversion layer between two barrier regions, resulting in a quantum well less than 15 nanometers wide. Source and drain regions adjacent to the barrier regions control current flow in and out of the quantum well. The GRTD may be integrated in CMOS ICs as a quantum dot or a quantum wire device. The GRTD may be operated in a negative conductance mode, in a charge pump mode and in a radiative emission mode.Type: ApplicationFiled: September 4, 2008Publication date: March 5, 2009Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Henry Litzmann Edwards, Chris Bowen, Tathagata Chatterjee
-
Publication number: 20090046823Abstract: A neutron generating device is described. In one embodiment, the device has a chamber filled with a gas containing deuterium or tritium together with a piezoelectric crystal having a mechanical excitation apparatus proximate thereto. The piezoelectric crystal has first and second metal electrodes located on opposing surfaces. The first metal electrode is in electrical contact with a neutral potential. A field emitter tip is located on the second metal electrode, which emits an electrical field to form deuterium or tritium ions upon the mechanical excitation of the piezoelectric crystal. The deuterium or tritium ions are accelerated by an electric potential differential between the first metal electrode and the second metal electrode into a target containing deuterium or tritium with sufficient energy to form neutrons.Type: ApplicationFiled: August 14, 2007Publication date: February 19, 2009Applicant: Texas Instruments IncorporatedInventors: Henry Litzmann Edwards, Tathagata Chatterjee
-
Patent number: 7466009Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.Type: GrantFiled: June 5, 2006Date of Patent: December 16, 2008Assignee: Texas Instruments IncorporatedInventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
-
Publication number: 20080277731Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Xiaoju Wu
-
Publication number: 20080096292Abstract: A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.Type: ApplicationFiled: October 20, 2006Publication date: April 24, 2008Inventors: Tathagata Chatterjee, Amitava Chatterjee
-
Publication number: 20080090346Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).Type: ApplicationFiled: November 1, 2007Publication date: April 17, 2008Applicant: Texas Instruments IncorporatedInventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
-
Patent number: 7312481Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).Type: GrantFiled: October 1, 2004Date of Patent: December 25, 2007Assignee: Texas Instruments IncorporatedInventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
-
Publication number: 20070281433Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.Type: ApplicationFiled: June 5, 2006Publication date: December 6, 2007Applicant: Texas Instruments IncorporatedInventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
-
Publication number: 20070210453Abstract: An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The dummy-fill-structures form a plurality of fiducials, each of the fiducials being located in a different region of the layer. Each fiducial comprises a pre-defined recognition pattern that is different from every other fiducial in adjacent regions of the layer.Type: ApplicationFiled: March 13, 2006Publication date: September 13, 2007Applicant: Texas Instruments Inc.Inventors: Jeffrey Large, Tathagata Chatterjee, Richard Irwin
-
Publication number: 20060071247Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).Type: ApplicationFiled: October 1, 2004Publication date: April 6, 2006Applicant: Texas Instruments IncorporatedInventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
-
Publication number: 20050127409Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.Type: ApplicationFiled: January 25, 2005Publication date: June 16, 2005Inventors: Henry Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
-
Patent number: 6867100Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.Type: GrantFiled: December 19, 2002Date of Patent: March 15, 2005Assignee: Texas Instruments IncorporatedInventors: Henry L. Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
-
Publication number: 20030151089Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.Type: ApplicationFiled: December 19, 2002Publication date: August 14, 2003Inventors: Henry L. Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland