Patents by Inventor Tathagata Chatterjee

Tathagata Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090061606
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well (240) within a substrate (210) and forming a suppression implant (420) within the substrate (210). The method for manufacturing the zener diode may further include forming a cathode (620) and an anode (520) within the substrate (210), wherein the suppression implant (420) is located proximate the doped well (240) and configured to reduce threading dislocations.
    Type: Application
    Filed: November 7, 2008
    Publication date: March 5, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: MARTIN MOLLAT, TATHAGATA CHATTERJEE, HENRY L. EDWARDS, LANCE S. ROBERTSON, RICHARD B. IRWIN, BINGHUA HU
  • Publication number: 20090056345
    Abstract: A nanoscale thermoelectric device, which may be operated as a refrigerator or as a thermoelectric generator includes N-type and p-type active areas connected to a central terminal and end electrodes made of interconnect metal. Reducing lateral dimensions of the active areas reduces vertical thermal conduction, thus improving the efficiency of the thermoelectric device. The thermoelectric device may be integrated into the fabrication process sequence of an IC without adding process cost or complexity. Operated as a refrigerator, the central terminal may be configured to cool a selected component in the IC, such as a transistor. Operated as a thermoelectric generator with a heat source applied to the central terminal, the end terminals may provide power to a circuit in the IC.
    Type: Application
    Filed: August 29, 2008
    Publication date: March 5, 2009
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: HENRY LITZMANN EDWARDS, TATHAGATA CHATTERJEE
  • Publication number: 20090046823
    Abstract: A neutron generating device is described. In one embodiment, the device has a chamber filled with a gas containing deuterium or tritium together with a piezoelectric crystal having a mechanical excitation apparatus proximate thereto. The piezoelectric crystal has first and second metal electrodes located on opposing surfaces. The first metal electrode is in electrical contact with a neutral potential. A field emitter tip is located on the second metal electrode, which emits an electrical field to form deuterium or tritium ions upon the mechanical excitation of the piezoelectric crystal. The deuterium or tritium ions are accelerated by an electric potential differential between the first metal electrode and the second metal electrode into a target containing deuterium or tritium with sufficient energy to form neutrons.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 19, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Henry Litzmann Edwards, Tathagata Chatterjee
  • Patent number: 7466009
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: December 16, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
  • Publication number: 20080277731
    Abstract: One embodiment of the present invention relates to a method for transistor matching. In this method, a channel is formed within a first transistor by applying a gate-source bias having a first polarity to the first transistor. The magnitude of a potential barrier in a pocket implant region of the first transistor is reduced by applying a body-source bias having the first polarity to the first transistor. Current flow is facilitated across the channel by applying a drain-source bias having the first polarity to the first transistor. Other methods and circuits are also disclosed.
    Type: Application
    Filed: May 10, 2007
    Publication date: November 13, 2008
    Inventors: Henry Litzmann Edwards, Tathagata Chatterjee, Mohamed Kamel Mahmoud, Xiaoju Wu
  • Publication number: 20080096292
    Abstract: A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.
    Type: Application
    Filed: October 20, 2006
    Publication date: April 24, 2008
    Inventors: Tathagata Chatterjee, Amitava Chatterjee
  • Publication number: 20080090346
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Application
    Filed: November 1, 2007
    Publication date: April 17, 2008
    Applicant: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Patent number: 7312481
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: December 25, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Publication number: 20070281433
    Abstract: The present invention provides a method for manufacturing a semiconductor device. In one embodiment, the method for manufacturing the semiconductor device includes a method for manufacturing a zener diode, including among others, forming a doped well within a substrate and forming a suppression implant within the substrate. The method for manufacturing the zener diode may further include forming a cathode and an anode within the substrate, wherein the suppression implant is located proximate the doped well and configured to reduce threading dislocations.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 6, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Martin Mollat, Tathagata Chatterjee, Henry L. Edwards, Lance S. Robertson, Richard B. Irwin, Binghua Hu
  • Publication number: 20070210453
    Abstract: An integrated circuit comprising interconnects located in a layer on a semiconductor substrate. The circuit also comprises dummy-fill-structures located between the interconnects in the layer. The dummy-fill-structures form a plurality of fiducials, each of the fiducials being located in a different region of the layer. Each fiducial comprises a pre-defined recognition pattern that is different from every other fiducial in adjacent regions of the layer.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 13, 2007
    Applicant: Texas Instruments Inc.
    Inventors: Jeffrey Large, Tathagata Chatterjee, Richard Irwin
  • Publication number: 20060071247
    Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).
    Type: Application
    Filed: October 1, 2004
    Publication date: April 6, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Kaiyuan Chen, Joe Trogolo, Tathagata Chatterjee, Steve Merchant
  • Publication number: 20050127409
    Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
    Type: Application
    Filed: January 25, 2005
    Publication date: June 16, 2005
    Inventors: Henry Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
  • Patent number: 6867100
    Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: March 15, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Henry L. Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
  • Publication number: 20030151089
    Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.
    Type: Application
    Filed: December 19, 2002
    Publication date: August 14, 2003
    Inventors: Henry L. Edwards, Sameer Pendharkar, Joe Trogolo, Tathagata Chatterjee, Taylor Efland
  • Patent number: 5932964
    Abstract: A light-emitting, specifically electroluminescent, europium-containing Group IIA fluoride epitaxial layer on silicon with a europium concentration in the range of from about 4 to about 40 wt % and a molecular beam epitaxy method for growth thereof are provided. Also provided is a light-emitting, specifically electroluminescent, device including a europium-containing Group IIA fluoride epitaxial layer on silicon with a europium concentration in the range of from about 4 to about 40 wt %. The Group IIA fluoride layer exhibits electroluminescence in the wavelength range of from about 450 to about 700 nm.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: August 3, 1999
    Assignee: McCann & Associates, Inc.
    Inventors: Patrick J. McCann, Xiao-Ming Fang, Tathagata Chatterjee