Patents by Inventor Tatsufumi Kurokawa

Tatsufumi Kurokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9493127
    Abstract: There is provided a semiconductor device including a power compensation circuit in an apparatus in order to notify of a power supply disconnection failure that a user of the apparatus may not recognize. The power compensation circuit includes a rectifier circuit and a detection circuit. The rectifier circuit is coupled between a first power supply line and a second power supply line. If the voltage of the second power supply line is lower than the voltage of the first power supply line by a predetermined value or more, the rectifier circuit supplies power from the first power supply line to the second power supply line. The detection circuit outputs a detection signal when the current flows through the rectifier circuit.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: November 15, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsufumi Kurokawa
  • Patent number: 9325168
    Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: April 26, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Patent number: 9231598
    Abstract: An integrated circuit device for use in an automobile. The integrated circuit device includes a first oscillator configured to generate a first clock signal, a second oscillator configured to generate a second clock signal, a comparator circuit configured to compare a frequency of the first clock signal with a frequency of the second clock signal, and configured to generate a selection signal for selecting either of the first clock signal or the second clock signal, and a selector configured to output an output clock signal that is selected from among a plurality of outputs including the first clock signal and the second clock signal in response to the select signal.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: January 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Koazechi, Tatsufumi Kurokawa
  • Publication number: 20150145561
    Abstract: An integrated circuit device for use in an automobile. The integrated circuit device includes a first oscillator configured to generate a first clock signal, a second oscillator configured to generate a second clock signal, a comparator circuit configured to compare a frequency of the first clock signal with a frequency of the second clock signal, and configured to generate a selection signal for selecting either of the first clock signal or the second clock signal, and a selector configured to output an output clock signal that is selected from among a plurality of outputs including the first clock signal and the second clock signal in response to the select signal.
    Type: Application
    Filed: February 2, 2015
    Publication date: May 28, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Shinichi KOAZECHI, Tatsufumi KUROKAWA
  • Patent number: 8970277
    Abstract: An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: March 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Koazechi, Tatsufumi Kurokawa
  • Publication number: 20150048874
    Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 19, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsufumi KUROKAWA
  • Patent number: 8901985
    Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: December 2, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Publication number: 20140240036
    Abstract: Disclosed is a semiconductor device that includes an N-channel MOS transistor and a control voltage generation circuit. The N-channel MOS transistor controls the supply of a power supply voltage obtained by stepping down a DC voltage. The control voltage generation circuit clips the gate voltage of the N-channel MOS transistor at a control voltage not higher than a predetermined voltage in accordance with the DC voltage.
    Type: Application
    Filed: December 5, 2013
    Publication date: August 28, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Tatsufumi KUROKAWA
  • Publication number: 20140239714
    Abstract: There is provided a semiconductor device including a power compensation circuit in an apparatus in order to notify of a power supply disconnection failure that a user of the apparatus may not recognize. The power compensation circuit includes a rectifier circuit and a detection circuit. The rectifier circuit is coupled between a first power supply line and a second power supply line. If the voltage of the second power supply line is lower than the voltage of the first power supply line by a predetermined value or more, the rectifier circuit supplies power from the first power supply line to the second power supply line. The detection circuit outputs a detection signal when the current flows through the rectifier circuit.
    Type: Application
    Filed: December 19, 2013
    Publication date: August 28, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Publication number: 20140232434
    Abstract: An integrated circuit device contains two oscillators to generate a first clock signal and a second clock signal. Along with comparing the frequencies of the first clock signal and the second clock signal, the integrated circuit device is configured to monitor whether or not each frequency is within the frequency tolerance range. The integrated circuit device selects an output clock signal from either of the first clock signal or the second clock signal according to results from comparing the frequencies of the first clock signal and the second clock signal and whether or not each of the first clock signal and the second clock signal are within the frequency tolerance range.
    Type: Application
    Filed: November 22, 2013
    Publication date: August 21, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Shinichi KOAZECHI, Tatsufumi KUROKAWA
  • Patent number: 8513984
    Abstract: A buffer circuit includes a first node that receives a first voltage, a second node, an output node that receives the first voltage, a first transistor coupled between the first node and the second node, the first transistor having a backgate receiving the first voltage, and a second transistor coupled between the second node and the output node, the second transistor having a backgate receiving a second voltage being higher than the first voltage.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: August 20, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Patent number: 8373452
    Abstract: A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: February 12, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Publication number: 20120286843
    Abstract: A P-channel MOS transistor MP1 is provided between an input voltage Vin and the low-voltage circuit. The cathode of a first zener diode Z1 is connected to a node between the input voltage Vin and the source of the P-channel MOS transistor MP1. The anode of the first zener diode Z1 is branched into two lines at a branch node N1, and one of the two lines is connected to a ground through a resistor R1. The other of the two lines is connected to the gate of the P-channel MOS transistor MP1. The cathode of a second zener diode Z2 is connected to a node between the low-voltage circuit and the drain of the P-channel MOS transistor MP1. The anode of the second zener diode Z2 is connected to a ground.
    Type: Application
    Filed: May 10, 2012
    Publication date: November 15, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsufumi KUROKAWA
  • Publication number: 20120187982
    Abstract: A buffer circuit includes a first node receiving a first voltage, a second node receiving a second voltage lower than the first voltage, a third node, an output node driving the first voltage and the second voltage, a first transistor coupled between the first node and the output node, a second transistor coupled between the second node and the output node, one end of the second transistor being connected to the second node, another end of the second transistor being connected to the third node, and a switch circuit coupled between the output node and the third node. Both of the first transistor and the switch circuit include a transistor having a first breakdown voltage. The second transistor has a second breakdown voltage being different from the first breakdown voltage.
    Type: Application
    Filed: April 2, 2012
    Publication date: July 26, 2012
    Applicant: Renesas Electronics Corporation
    Inventor: Tatsufumi KUROKAWA
  • Patent number: 8174296
    Abstract: A buffer circuit includes a first power source node receiving a first voltage, a second power source node receiving a second voltage lower than the first voltage, an output node driving the first and second voltage, a first transistor coupled between the first power source node and the output node, the first transistor being controlled by a first voltage swing, a second transistor coupled between the second power source node and the output node, the second transistor being controlled by a second voltage swing smaller than the first voltage swing and a switch circuit coupled between the output node and the second transistor, the switch circuit being controlled by a third voltage swing larger than the second voltage swing.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: May 8, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Publication number: 20110285425
    Abstract: A buffer circuit includes a first power source node receiving a first voltage, a second power source node receiving a second voltage lower than the first voltage, an output node driving the first and second voltage, a first transistor coupled between the first power source node and the output node, the first transistor being controlled by a first voltage swing, a second transistor coupled between the second power source node and the output node, the second transistor being controlled by a second voltage swing smaller than the first voltage swing and a switch circuit coupled between the output node and the second transistor, the switch circuit being controlled by a third voltage swing larger than the second voltage swing.
    Type: Application
    Filed: July 29, 2011
    Publication date: November 24, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Tatsufumi Kurokawa
  • Patent number: 8008952
    Abstract: A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 30, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Publication number: 20100244904
    Abstract: A buffer circuit outputs a low voltage and high voltages as opposed logic signals and a first high voltage and a second high voltage that is higher than the first high voltage as the high voltages.
    Type: Application
    Filed: March 2, 2010
    Publication date: September 30, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Patent number: 7385444
    Abstract: The class D amplifier comprises a voltage control current source circuit for current-converting the voice voltage signal Vsin of the input into two signals with different polarities, two capacitance elements for integration where the electric charges of the each current-converted signal and the feedback signal are stored respectively, two hysteresis comparators for PWM conversion for comparing the potentials of the two capacitance elements for integration and a reference potential Vcom respectively, two output buffers for amplifying the outputs thereof respectively, and two constant current source feedback circuits for feeding back the output thereof respectively.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: June 10, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Tatsufumi Kurokawa
  • Patent number: 7312657
    Abstract: The class D amplifier according to an embodiment of the invention comprises a voltage control current source circuit for current—converting voice voltage signals Sin to be input to two signals with different polarities, capacitance elements for integration for storing the electric charge of each of the current—converted signals and feedback signals respectively, hysteresis comparators for PWM conversion for comparing the potential of the capacitance elements for integration and reference potential respectively, output buffers for amplifying the output thereof respectively, and constant current source feedback circuits for feeding back the output thereof respectively.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: December 25, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Tatsufumi Kurokawa