Patents by Inventor Tatsunori Kanai

Tatsunori Kanai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10803683
    Abstract: An information processing device according to an embodiment includes a storage device and one or more processors configured to function as a setting unit and a record control unit. The setting unit sets a record level of history information according to a reliability of derivative information derived from output information of a sensor. The record control unit performs control to store the history information in the storage device according to the record level.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: October 13, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Segawa, Tatsunori Kanai, Takashi Yoshikawa
  • Patent number: 10725876
    Abstract: According to an embodiment, an electronic circuit board includes a nonvolatile memory, a reading circuit to read data stored in the nonvolatile memory, a switch, and a communication circuit. When power is supplied from a first power source, the switch performs switching to a first state in which the nonvolatile memory and a host device configured to read and write data from and in the nonvolatile memory are connected. When power is supplied from a second power source, the switch performs switching to a second state in which the host device and the nonvolatile memory are not connected and the reading circuit and the nonvolatile memory are connected. The communication circuit transmits, to an external device, the data read by the reading circuit from the nonvolatile memory when power is being supplied from the second power source.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: July 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsunori Kanai, Tetsuro Kimura, Yusuke Shirota, Masaya Tarui
  • Patent number: 10725675
    Abstract: According to an embodiment, a management apparatus manages access to a plurality of types of storage units by a processing circuit. Each of the plurality of types of storage units includes a plurality of first regions, and each of the plurality of first regions includes a plurality of second regions. The management apparatus includes a circuitry configured to function as a management unit. The management unit manages a management table in which identification information of one or more of the plurality of first regions and access management information defining access information indicating whether or not each second region included in the one or more of the plurality of first regions is accessed by the processing circuit are associated with each other.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 28, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Yusuke Shirota
  • Patent number: 10719247
    Abstract: An information processing device according to an embodiment includes a processing circuit. The processing circuit is configured to: obtains operation information; estimates, based on the obtained operation information, the execution performance of memory accesses with respect to a first memory and a nonvolatile memory unit in the case in which a managing device performs operations according to each of a plurality of memory control methods; selects, based on the execution performance estimated for each memory control method, any one memory control method from among a plurality of memory control methods; and performs a setting operation with respect to an access managing unit in such a way that the managing device accesses the first memory and the nonvolatile memory unit according to the selected memory control method.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: July 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Mayuko Koezuka, Tatsunori Kanai
  • Patent number: 10719436
    Abstract: According to an embodiment, a management device includes a counter storage unit, a first management information storage unit, and an update unit. The first management information storage unit stores a first management table capable of storing first management information about each of a predetermined number of first areas. The first management information indicates whether each second area included in a corresponding first area has data written therein. In response to writing of first data into the nonvolatile memory, when a state of a target second area indicated in the first management information about a target first area is an unwritten state, the update unit changes the state of the target second area to a written state; while when the state of the target second area indicated in the first management information is the written state, the update unit updates the counter value for the target first area.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 21, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shiyo Yoshimura, Tatsunori Kanai, Yusuke Shirota, Satoshi Shirai
  • Patent number: 10649694
    Abstract: A management device is configured to control reading and writing of data as performed by a processing circuit with respect to a nonvolatile memory. The management device includes circuitry configured to: in response to a request from the processing circuit, perform writing or reading with respect to the nonvolatile memory; in response to writing with respect to the nonvolatile memory, update a table indicating a rewriting count for each area in the nonvolatile memory; detect writing having a high degree of locality representing rewriting operation performed to an extent equal to or greater than a reference value, with respect to the same area in the nonvolatile memory by refer to the table; and identify an area under attack in which the writing having the high degree of locality is performed.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: May 12, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Tatsunori Kanai
  • Publication number: 20200143275
    Abstract: According to an embodiment, an information processing device includes a hardware processor configured to function as: an acquisition unit configured to acquire operation statistical information on a processing circuit; a derivation unit configured to derive a memory access characteristic of the processing circuit from the acquired operation statistical information, based on a prediction model for deriving the memory access characteristic from the operation statistical information; and a determination unit configured to determine an access method from among a first access method and a second access method based on the derived memory access characteristic, the first access method transferring data in a second memory unit to a first memory unit and accessing the data in the first memory unit, the second access method accessing data in the second memory unit, an access speed of the second memory unit from the processing circuit being slower than that of the first memory unit.
    Type: Application
    Filed: August 29, 2019
    Publication date: May 7, 2020
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Tatsunori Kanai
  • Patent number: 10635587
    Abstract: According to one embodiment, a memory controller includes a nonvolatile cache memory and a controller. The nonvolatile cache memory is configured to store a piece of data stored in a nonvolatile main memory connected to the memory controller. The controller is configured to control writing of data to the nonvolatile cache memory. The memory controller is connected to a processor via an interconnect that ensures a protocol indicating a procedure for preventing data inconsistency in a plurality of cache memories. The controller causes, after detecting that the processor has updated data corresponding to any area of the nonvolatile main memory using the protocol, the updated data to be transmitted to the memory controller and writes the updated data to the nonvolatile cache memory.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: April 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Masaya Tarui
  • Patent number: 10606517
    Abstract: According to an embodiment, a management device includes: a setting memory configured to store an access method indicating which of a first access process of performing writing or reading with respect to data transferred from a non-volatile memory to a first memory, or a second access process of directly performing writing or reading with respect to data stored in the non-volatile memory, is to be executed for each of the plurality of pages; and circuitry configured to select any page set to the second access process among the plurality of pages, as an exchange target page, when a write amount with respect to the non-volatile memory is larger than a set value, and change an access method of the exchange target page from the second access process to the first access process.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: March 31, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke Shirota, Mayuko Koezuka, Tatsunori Kanai
  • Publication number: 20200089426
    Abstract: According to an embodiment, a management device is for controlling readout and writing of data that are performed by a processing circuit with respect to a non-volatile memory storing a plurality of pages. The non-volatile memory includes a high-temperature region and a low-temperature region in which temperature is relatively lower than in the high-temperature region during operation. The management device includes one or more processors configured to move storage positions of the plurality of pages in such a manner that pages included in a high access page group are stored more in the low-temperature region than in the high-temperature region in the voluntary memory, where the plurality of pages are classified into the high access page group in which access amounts are relatively high, and a low access page group in which access amounts are relatively low.
    Type: Application
    Filed: February 27, 2019
    Publication date: March 19, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke SHIROTA, Tatsunori KANAI
  • Publication number: 20200081634
    Abstract: An information processing apparatus according to an embodiment includes a first memory, a non-volatile memory, and one or more processors. The processor is configured to execute information processing on data stored in those memories. The processor allocates, to each of pages included in a file stored in the non-volatile memory by executing an operating system, a memory access method that indicates either copy access processing or direct access processing to be executed. The copy access processing performs writing and readout of data copied from the non-volatile memory into the first memory. The direct access processing directly performs writing and readout of data stored in the non-volatile memory. The processor accesses those memories by the memory access method allocated to each of the pages included in the file when the operating system receives a request from an application program for writing or readout on the file.
    Type: Application
    Filed: February 27, 2019
    Publication date: March 12, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsunori KANAI, Yusuke SHIROTA
  • Patent number: 10438665
    Abstract: According to one embodiment, a memory device is connected to one or more information processing devices. The memory device includes a shared memory and a memory controller. The memory controller is configured to analyze an access to the shared memory by the one or more information processing devices and decide on an access method for accessing the shared memory by the one or more information processing devices. The memory controller is configured to give an instruction indicating the decided access method to the one or more information processing devices.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: October 8, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Yusuke Shirota, Tatsunori Kanai, Satoshi Shirai
  • Publication number: 20190294355
    Abstract: An information processing device according to an embodiment includes a processing circuit. The processing circuit is configured to: obtains operation information; estimates, based on the obtained operation information, the execution performance of memory accesses with respect to a first memory and a nonvolatile memory unit in the case in which a managing device performs operations according to each of a plurality of memory control methods; selects, based on the execution performance estimated for each memory control method, any one memory control method from among a plurality of memory control methods; and performs a setting operation with respect to an access managing unit in such a way that the managing device accesses the first memory and the nonvolatile memory unit according to the selected memory control method.
    Type: Application
    Filed: August 30, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke SHIROTA, Mayuko KOEZUKA, Tatsunori KANAI
  • Publication number: 20190294989
    Abstract: A model generation apparatus according to an embodiment includes a processor circuit. The processor circuit is configured to: divide time-series data of operation information in a time direction to generate a plurality of segments; allocate any one memory control method of a plurality of memory control methods to each of the plurality of segments; estimate, for each of the plurality of segments, execution performance of memory access that is obtainable in a case where an information processing apparatus executes processing of a corresponding segment by an allocated memory control method; select a plurality of training segments from among the plurality of segments; and generate a decision model based on the selected plurality of training segments.
    Type: Application
    Filed: August 30, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mayuko KOEZUKA, Yusuke SHIROTA, Tatsunori KANAI
  • Publication number: 20190286367
    Abstract: According to an embodiment, a management device includes: a setting memory configured to store an access method indicating which of a first access process of performing writing or reading with respect to data transferred from a non-volatile memory to a first memory, or a second access process of directly performing writing or reading with respect to data stored in the non-volatile memory, is to be executed for each of the plurality of pages; and circuitry configured to select any page set to the second access process among the plurality of pages, as an exchange target page, when a write amount with respect to the non-volatile memory is larger than a set value, and change an access method of the exchange target page from the second access process to the first access process.
    Type: Application
    Filed: August 29, 2018
    Publication date: September 19, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Shirota, Mayuko Koezuka, Tatsunori Kanai
  • Publication number: 20190286347
    Abstract: According to an embodiment, a management apparatus manages access to a plurality of types of storage units by a processing circuit. Each of the plurality of types of storage units includes a plurality of first regions, and each of the plurality of first regions includes a plurality of second regions. The management apparatus includes a circuitry configured to function as a management unit. The management unit manages a management table in which identification information of one or more of the plurality of first regions and access management information defining access information indicating whether or not each second region included in the one or more of the plurality of first regions is accessed by the processing circuit are associated with each other.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 19, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori KANAI, Yusuke SHIROTA
  • Publication number: 20190286368
    Abstract: A management device is configured to control reading and writing of data as performed by a processing circuit with respect to a nonvolatile memory. The management device includes circuitry configured to: in response to a request from the processing circuit, perform writing or reading with respect to the nonvolatile memory; in response to writing with respect to the nonvolatile memory, update a table indicating a rewriting count for each area in the nonvolatile memory; detect writing having a high degree of locality representing rewriting operation performed to an extent equal to or greater than a reference value, with respect to the same area in the nonvolatile memory by refer to the table; and identify an area under attack in which the writing having the high degree of locality is performed.
    Type: Application
    Filed: August 30, 2018
    Publication date: September 19, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke SHIROTA, Tatsunori KANAI
  • Patent number: 10379746
    Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, and a second memory. The processing device executes first processing on first data. The second memory stores the first data and has a data access latency higher than that of the first memory. The first data includes first and second pages, the first page being read/written times not less than a threshold in a certain period shorter than a period for executing the first processing, the second page being read/written times less than the threshold in the certain period. The processing device includes a controller configured to execute first access to move the first page to the first memory and then read/write data from/to the moved first page, and execute second access to directly read/write data from/to the second page of the second memory.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura
  • Patent number: 10353454
    Abstract: According to an embodiment, an information processing apparatus includes a processing device, a first memory, a second memory, and a controller. The processing device is configured to process first data. The first memory is configured to store at least part of the first data and has an active region supplied with power necessary for holding data. The second memory is configured to store part of the first data. The controller is configured to change number of active regions such that processing information is not more than a threshold. The processing information indicates an amount of processing for moving at least part of second data stored in the first memory to the second memory and for moving at least part of third data stored in the second memory to the first memory, in a certain period for processing the first data having a size larger than active regions.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Shiyo Yoshimura, Satoshi Shirai
  • Patent number: 10356320
    Abstract: According to an embodiment, in an information processing device, when there is no change in a first image received from an image sensor, reception of the next first image is awaited. When there is a change in the first image, a second image having a higher resolution than the first image is received from the image sensor and processing for the second image is performed.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yusuke Shirota, Tatsunori Kanai, Junichi Segawa, Toshiki Kizu, Akira Takeda