Abstract: A semiconductor device comprises a central processing device, a first logical circuit, and a serial memory interface circuit. The first logical circuit has a first scan chain in which a first scan pattern is set, is configured to suppress a leakage current when the first scan pattern for power saving is set in the first scan chain. The serial memory interface circuit is configured to acquire the first scan pattern for power saving from an external storage device. The leakage current of the first logical circuit is suppressed by transferring the first scan pattern for power saving acquired by the serial memory interface circuit to the first logical circuit and setting the first scan pattern for power saving in the first scan chain under control of the central processing device.

Abstract: A semiconductor device comprises a central processing device, a first logical circuit, and a serial memory interface circuit. The first logical circuit has a first scan chain in which a first scan pattern is set, is configured to suppress a leakage current when the first scan pattern for power saving is set in the first scan chain. The serial memory interface circuit is configured to acquire the first scan pattern for power saving from an external storage device. The leakage current of the first logical circuit is suppressed by transferring the first scan pattern for power saving acquired by the serial memory interface circuit to the first logical circuit and setting the first scan pattern for power saving in the first scan chain under control of the central processing device.

Abstract: A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.

Abstract: Provided is a secondary battery which is small in size and in which current capacity per unit volume can be increased. The present invention provides a secondary battery including two cell units each including a charging layer between a first electrode layer and a second electrode layer, the two cell units being parallel-connected by juxtaposing and connecting a first electrode layer of one cell unit and a first electrode layer of the other cell unit or a second electrode layer of the one cell unit and a second electrode layer of the other cell unit, and by wire-connecting the second electrode layer of the one cell unit and the second electrode layer of the other cell unit or the first electrode layer of the one cell unit and the first electrode layer of the other cell unit.

Abstract: A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer.

Abstract: A method for manufacturing oxide semiconductor secondary cells concurrently and evenly on a plurality of chips. A method for manufacturing a chip on which an oxide semiconductor secondary cell is mounted, the oxide semiconductor secondary cell that is formed by layering a first electrode, a charging function layer, and a second electrode being layered on a circuit. The method includes a layering process to layer and form the oxide semiconductor secondary cells integrally at regions corresponding to a plurality of chips formed on a wafer without separately forming oxide semiconductor secondary cells at regions corresponding to the respective chips, and a separating process to perform separation into individual oxide semiconductor secondary cells corresponding to the respective chips by performing pattern etching on the integrally-formed oxide semiconductor secondary cells to eliminate regions not corresponding to the respective chips except for regions corresponding to the respective chips.

Abstract: A structure with suppressed thickness and high-density when battery cells of a thin-film-solid secondary battery are stacked. Adjacent battery cells are stacked such that negative electrodes are in contact with each other and positive electrodes are in contact with each other, and arranged such that a taking-out lead electrode smaller than negative or positive electrode surfaces are sandwiched between two negative electrodes in contact with each other or two positive electrodes in contact with each other, and the lead electrodes sandwiched between electrodes of different layers are arranged such that there is no region where all of the lead electrodes simultaneously overlap one another as viewed in a planar arrangement. There are a strip-shaped lead electrode and a linear lead electrode. Further, a conductive sheet forming the electrode is extended to also serve as the taking-out electrode, thereby making it possible to reduce the number of lead electrodes.

Abstract: A multi-layer wiring board includes wiring layers stacked on a substrate with an insulating layer between each layer. A wire formed in the wiring layer consists of a first layer and a second layer to form a double layered structure. The first layer is made of a first conductive material and the second layer is made of a second conductive material having relative magnetic permeability of 10 or more and larger than that of the first conductive material. The characteristic impedance of the wire is adjusted to a value closer to 50 ohms than that of a wire which has the same thickness as of the wire with the double layered structure, and is made only of the first conductive material.

Abstract: An apparatus includes a wiring base plate arranged on an upper side of a chuck top and having a wiring path connected to a tester, a probe card having a probe board spaced from the wiring base plate with a first surface thereof opposed to the wiring base plate and having a wiring path corresponding to the wiring path and probes provided on a second surface of the probe board to be connected to the wiring path and enabling to respectively contact connection pads of a semiconductor wafer on the chuck top, and an electric connector connecting the wiring base plate to the probe board by low heat conduction supporting members and decreasing heat conduction therebetween and electrically connecting the wiring paths.

Abstract: An apparatus includes a probe card having a probe board with a conductive path electrically connected to a tester and probes enabling to respectively contact connection pads of a semiconductor wafer on a chuck top and moving relatively to the chuck top, and an elastic heat conducting member arranged between a working surface of the chuck top or the semiconductor wafer on the working surface and the probe board. The elastic heat conducting member can abut on the working surface of the chuck top or the semiconductor wafer on the working surface and the probe board when the probes do not abut on the respective corresponding connection pads and is elastically deformable not to prevent abutment between the probes and the respective corresponding connection pads.

Abstract: A secondary battery-mounted circuit chip wherein secondary battery is directly fabricated on opposed surface of formed circuit into an integrated structure of the secondary battery and circuit, and a manufacturing method thereof. Secondary battery-mounted circuit chip is configured such that secondary battery is directly fabricated in region corresponding to circuit into integrated structure of secondary battery and circuit. The chip is secondary battery-mounted circuit chip wherein secondary battery is formed on surface opposing a circuit region fabricated on wafer.

Abstract: A probe card for an electric test of a device under test on a working table incorporating a heat source includes a circuit base plate including conductive paths connected to a tester, a probe base plate including conductive paths corresponding to the conductive paths and provided with probes connected to the conductive paths, and a heat expansion adjusting member bonded to the probe base plate, having a different linear expansion coefficient from that of the probe base plate to restrain heat expansion of the probe base plate, and constituting a composite body with the probe base plate. In a case where, when the device under test is at two measuring temperatures, the composite body is at corresponding achieving temperatures, expansion changing amounts of the device under test and the composite body under temperature differences between the respective measuring temperatures and the corresponding achieving temperatures are set to be approximately equal.

Abstract: A structure with suppressed thickness and high-density when battery cells of a thin-film-solid secondary battery are stacked. Adjacent battery cells are stacked such that negative electrodes are in contact with each other and positive electrodes are in contact with each other, and arranged such that a taking-out lead electrode smaller than negative or positive electrode surfaces are sandwiched between two negative electrodes in contact with each other or two positive electrodes in contact with each other, and the lead electrodes sandwiched between electrodes of different layers are arranged such that there is no region where all of the lead electrodes simultaneously overlap one another as viewed in a planar arrangement. There are a strip-shaped lead electrode and a linear lead electrode. Further, a conductive sheet forming the electrode is extended to also serve as the taking-out electrode, thereby making it possible to reduce the number of lead electrodes.

Abstract: Provided is a secondary battery which is small in size and in which current capacity per unit volume can be increased. The present invention provides a secondary battery including two cell units each including a charging layer between a first electrode layer and a second electrode layer, the two cell units being parallel-connected by juxtaposing and connecting a first electrode layer of one cell unit and a first electrode layer of the other cell unit or a second electrode layer of the one cell unit and a second electrode layer of the other cell unit, and by wire-connecting the second electrode layer of the one cell unit and the second electrode layer of the other cell unit or the first electrode layer of the one cell unit and the first electrode layer of the other cell unit.

Abstract: The object of the present invention is to provide a multi-layer wiring board which is easy to adjust the characteristic impedance and is able to adapt to the narrow-pitch tendency of terminals, and a process for manufacturing the same.

Abstract: An apparatus includes a wiring base plate arranged on an upper side of a chuck top and having a wiring path connected to a tester, a probe card having a probe board spaced from the wiring base plate with a first surface thereof opposed to the wiring base plate and having a wiring path corresponding to the wiring path and probes provided on a second surface of the probe board to be connected to the wiring path and enabling to respectively contact connection pads of a semiconductor wafer on the chuck top, and an electric connector connecting the wiring base plate to the probe board by low heat conduction supporting members and decreasing heat conduction therebetween and electrically connecting the wiring paths.

Abstract: An apparatus includes a probe card having a probe board with a conductive path electrically connected to a tester and probes enabling to respectively contact connection pads of a semiconductor wafer on a chuck top and moving relatively to the chuck top, and an elastic heat conducting member arranged between a working surface of the chuck top or the semiconductor wafer on the working surface and the probe board. The elastic heat conducting member can abut on the working surface of the chuck top or the semiconductor wafer on the working surface and the probe board when the probes do not abut on the respective corresponding connection pads and is elastically deformable not to prevent abutment between the probes and the respective corresponding connection pads.

Abstract: A probe card for an electric test of a device under test on a working table incorporating a heat source includes a circuit base plate including conductive paths connected to a tester, a probe base plate including conductive paths corresponding to the conductive paths and provided with probes connected to the conductive paths, and a heat expansion adjusting member bonded to the probe base plate, having a different linear expansion coefficient from that of the probe base plate to restrain heat expansion of the probe base plate, and constituting a composite body with the probe base plate. In a case where, when the device under test is at two measuring temperatures, the composite body is at corresponding achieving temperatures, expansion changing amounts of the device under test and the composite body under temperature differences between the respective measuring temperatures and the corresponding achieving temperatures are set to be approximately equal.

Abstract: A computer program generates a wire routing pattern that connects one driver with a plurality of receivers. The overlapping length of each vector pair, which consists of any two vectors headed from the driver to the receivers, is calculated. One vector pair that has the greatest overlapping length is selected. For the selected vector pair, three kinds of common nodes are created, each of which is used to make a common path part of the way to the receivers, to generate three kinds of renewed vector patterns. The operations are repeated and plural candidate routing patters are acquired. One candidate routing pattern having the smallest total wiring length is selected as the optimum routing pattern. If there exist plural patterns that have the same smallest total wiring length, one pattern can be selected that has the smallest one of the greatest. D-R path lengths.

Abstract: A recipe providing system and a recipe providing method for presenting a suitable recipe that matches to a user request on specific foodstuff basis and/or specific cooking process basis. A recipe element storing unit stores a recipe element data related to recipes. The recipe elements are hierarchized according to cooking process of one recipe and each of the recipe element has link information to a finished-dish for which the recipe element is used. A recipe generating means retrieves/extracts recipe element data from the recipe element storing unit in accordance with user's recipe request, and generates a recipe. A recipe sending means sends the recipe generated by the recipe generating means to users.