Patents by Inventor Tatsuo Nakayama

Tatsuo Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410868
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 10388779
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 20, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 10249715
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hironobu Miyamoto, Tatsuo Nakayama, Atsushi Tsuboi, Yasuhiro Okamoto, Hiroshi Kawaguchi
  • Patent number: 10243070
    Abstract: A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an electron supply layer, a mesa type cap layer, a source electrode, a drain electrode and a gate insulating film covering the cap layer, and a gate electrode formed on the gate insulating film, is configured as follows. The cap layer and the gate electrode are separated from each other by the gate insulating film, and side surfaces of the cap layer, the side surfaces being closer to the drain electrode and the source electrode, have tapered shapes. For example, a taper angle (?1) of the side surface of the cap layer (mesa portion) is equal to or larger than 120 degrees. By this configuration, a TDDB life can be effectively improved, and variation in an ON-resistance can be effectively suppressed.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: March 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hironobu Miyamoto, Yasuhiro Okamoto, Hiroshi Kawaguchi, Tatsuo Nakayama
  • Patent number: 10199476
    Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: February 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto
  • Publication number: 20190019886
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO
  • Patent number: 10134908
    Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 20, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto
  • Patent number: 10109730
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 10084077
    Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Miyake, Tatsuo Nakayama
  • Publication number: 20180233590
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Application
    Filed: March 16, 2018
    Publication date: August 16, 2018
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Patent number: 10050142
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 14, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
  • Publication number: 20180219089
    Abstract: A mesa portion of a semiconductor device, which includes a channel base layer formed of a first nitride semiconductor layer, a channel layer formed of a second nitride semiconductor layer, a barrier layer formed of a third nitride semiconductor layer, a mesa-type fourth nitride semiconductor layer, a gate insulating film that covers the mesa portion, and a gate electrode formed over the gate insulating film, is used as a co-doped layer. The mesa portion is used as the co-doped layer, so that interface charges generated at an interface between the gate insulating film and the mesa portion can be cancelled by p-type impurity or n-type impurity in the co-doped layer and a threshold potential can be improved. Further, the fourth nitride semiconductor layer is n-type until the gate insulating film is formed, and the fourth nitride semiconductor layer is made neutral or p-type after the gate insulating film is formed.
    Type: Application
    Filed: December 14, 2017
    Publication date: August 2, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO
  • Patent number: 10014403
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 3, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Publication number: 20180151377
    Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.
    Type: Application
    Filed: January 29, 2018
    Publication date: May 31, 2018
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 9984884
    Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hiroshi Kawaguchi, Toshiyuki Takewaki, Nobuhiro Nagura, Takayuki Nagai, Yoshinao Miura, Hironobu Miyamoto
  • Patent number: 9985108
    Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1-x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<x?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: May 29, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Masaaki Kanazawa, Yasuhiro Okamoto, Takashi Inoue, Hironobu Miyamoto, Ryohei Nega
  • Patent number: 9978642
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a barrier layer on a substrate. A trench extends to a certain depth of the channel layer through the barrier layer. A gate electrode is disposed on a gate insulating film within the trench. A source electrode and a drain electrode are provided on the two respective sides of the gate electrode. A coupling within a through-hole that extends to the voltage clamp layer electrically couples the voltage clamp layer to the source electrode. An impurity region containing an impurity having an acceptor level deeper than that of a p-type impurity is provided under the through-hole. The voltage clamp layer decreases variations in characteristics such as threshold voltage and on resistance. The contact resistance is reduced through hopping conduction due to the impurity in the impurity region.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 9954087
    Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: April 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
  • Publication number: 20180076312
    Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventors: Shinichi MIYAKE, Tatsuo NAKAYAMA
  • Publication number: 20180061983
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.
    Type: Application
    Filed: October 20, 2017
    Publication date: March 1, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI