Patents by Inventor Tatsuro Hiruta

Tatsuro Hiruta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10299381
    Abstract: According to one embodiment, an electronic device includes a substrate including a first face, a plurality of first conductors on the first face, a plurality of second conductors on the first face, and a first electronic component mounted on the first face, and including a first terminal connected to the plurality of first conductors, and a second terminal connected to the plurality of second conductors.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: May 21, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Naoki Kimura, Tatsuro Hiruta
  • Patent number: 9831150
    Abstract: According to one embodiment, a semiconductor device includes a first substrate, a second substrate, a first electronic component, a heat-conducting layer, a covering portion, and a heat-transporting portion. The first substrate has a first face and the second substrate has a second face and a third face. The first electronic component has a fourth face and a fifth face. The heat-conducting layer covers the third face and the fifth face. The covering portion covers at least the heat-conducting layer. The heat-transporting portion thermally connects the heat-conducting layer and the first substrate, and is located outside the second substrate and outside the covering portion.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: November 28, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Tatsuro Hiruta
  • Publication number: 20170064833
    Abstract: According to one embodiment, an electronic device includes a substrate including a first face, a plurality of first conductors on the first face, a plurality of second conductors on the first face, and a first electronic component mounted on the first face, and including a first terminal connected to the plurality of first conductors, and a second terminal connected to the plurality of second conductors.
    Type: Application
    Filed: March 1, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Naoki KIMURA, Tatsuro HIRUTA
  • Publication number: 20160293513
    Abstract: A semiconductor device includes a first substrate including a surface layer and a ground layer, the surface layer including a plurality of first vias that is exposed on a surface of the first substrate and electrically connected to the ground layer, a second substrate disposed on the first substrate and including a plurality of second vias penetrating through the second substrate, a plurality of conduction elements, each disposed between one of the first vias and one of the second vias, a semiconductor device unit disposed on the second substrate, and a heat transfer layer covering the semiconductor device unit and in contact with the second vias at a periphery of the semiconductor device unit, such that heat generated by the semiconductor device unit is transferred to the ground layer, through the heat transfer layer, the second vias, the conduction elements, and the first vias.
    Type: Application
    Filed: August 27, 2015
    Publication date: October 6, 2016
    Inventor: Tatsuro HIRUTA
  • Publication number: 20160268179
    Abstract: According to one embodiment, a semiconductor device includes a first substrate, a second substrate, a first electronic component, a heat-conducting layer, a covering portion, and a heat-transporting portion. The first substrate has a first face and the second substrate has a second face and a third face. The first electronic component has a fourth face and a fifth face. The heat-conducting layer covers the third face and the fifth face. The covering portion covers at least the heat-conducting layer. The heat-transporting portion thermally connects the heat-conducting layer and the first substrate, and is located outside the second substrate and outside the covering portion.
    Type: Application
    Filed: January 28, 2016
    Publication date: September 15, 2016
    Inventor: Tatsuro Hiruta