Abstract: According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.

Abstract: According to one embodiment, a semiconductor device includes a first insulating layer on an underlying layer, a first trench formed in the first insulating layer, and a first graphene layer provided in the first trench. The first trench comprises a bottom surface on the underlying and two side surfaces joined to the bottom surface, formed into a U-shape. The first graphene layer has a stacked structure including a plurality of graphene sheets. The plurality of graphene sheets each include a depression in a central portion. Portions of the graphene sheets located in an edge of the first graphene layer are each extended upward, which is in a direction opposite to the bottom surface.

Abstract: According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.

Abstract: According to one embodiment, a semiconductor device includes a first insulating layer on an underlying layer, a first trench formed in the first insulating layer, and a first graphene layer provided in the first trench. The first trench comprises a bottom surface on the underlying and two side surfaces joined to the bottom surface, formed into a U-shape. The first graphene layer has a stacked structure including a plurality of graphene sheets. The plurality of graphene sheets each include a depression in a central portion. Portions of the graphene sheets located in an edge of the first graphene layer are each extended upward, which is in a direction opposite to the bottom surface.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a graphene film on a catalytic layer, removing a part of the graphene film to form an exposed side surface of the graphene film, introducing dopant into the graphene film from the exposed side surface, and forming a graphene interconnect by patterning the graphene film into which the dopant is introduced.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer thereon. The catalyst layer includes a first to fifth catalyst regions arranged along a first direction in order of the first to fifth catalyst regions. The first, third and fifth catalyst regions include upper surfaces higher than those of the second and fourth catalyst regions. Adjacent ones of the first to fifth catalyst regions are in contact with each other. A distance between the first and the third catalyst region and a distance between the third and fifth catalyst region are greater than a mean free path of graphene. The graphene layer includes a first graphene layer on the second catalyst region and a second graphene layer on the fourth catalyst region.

Abstract: According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.

Abstract: The sensor includes a first graphene film that is provided on the insulating layer so as to be located in a flow path of a liquid containing the detection target substance, the first graphene film having a first edge that is parallel with a first direction that is along the flow path and a first edge that is parallel with a second direction that is different from the first direction, and the first graphene film having the shape of a band that extends in the second direction. The sensor includes a first electrode that is electrically connected to the first edge of the first graphene film that is parallel with the first direction. The sensor includes a second electrode that is electrically connected to a second edge of the first graphene film that is opposed to the first edge that is parallel with the first direction.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device, the method includes forming a first film having a first melting point, forming a pattern of a second film on an upper surface of the first film, the second film having a second melting point lower than the first melting point, and forming a graphene film on the upper surface of the first film, the graphene film being formed from a side surface of the pattern of the second film.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a first interconnect, and an insulating film provided on the first interconnect, and being with a through hole communicating with the first interconnect. A catalyst layer is provided on the first interconnect of a bottom portion of the through hole. The catalyst layer has a form of a continuous film, and includes catalyst material and impurity. A first plug is provided in the through hole and is in contact with the catalyst layer, and includes a carbon nanotube layer. A second interconnect is disposed above the first interconnect and connected to the first interconnect via the first plug.

Abstract: According to one embodiment, a semiconductor device is disclosed. The device includes a foundation layer including first and second layers being different from each other in material, and the foundation layer including a surface on which a boundary of the first and second layers is presented, a catalyst layer on the surface of the foundation layer, and the catalyst layer including a protruding area. The device further includes a graphene layer being in contact with the protruding area.

Abstract: A vehicle diagnostic system capable of diagnosing ECUs for partial networking includes a communication bus mounted on a vehicle, a plurality of controllers for controlling vehicle operations, and a diagnostic equipment to collect diagnostic information from the controllers through the communication bus and to diagnose the vehicle operations. The controllers are connected with each other through the communication bus. Each of controllers operates in a normal mode and in a sleep mode, the sleep mode being an operation mode in which all of or a part of the functions excluding at least a function for receiving an wake-up instruction to return to the normal mode through the communication bus are suspended. At least one of the controllers is configured to send the wake-up instruction to all the other controllers in response to receiving a predetermined signal from the diagnostic equipment.

Abstract: According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.

Abstract: According to one embodiment, a graphene interconnection includes an insulating film, a catalyst film, and a graphene layer. An insulating film includes an interconnection trench. A catalyst film is formed in the interconnection trench and filling at least a portion of the interconnection trench. A graphene layer is formed on the catalyst film in the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to a bottom surface of the interconnection trench.

Abstract: According to one embodiment, a semiconductor device using multi-layered graphene wires includes a substrate having semiconductor elements formed therein, a first graphene wire formed above the substrate and including a multi-layered graphene layer having a preset impurity doped therein, a second graphene wire formed on the same layer as the first multi-layered graphene wire above the substrate and including a multi-layered graphene layer into which the preset impurity is not doped, a lower-layer contact connected to the undersurface side of the first multi-layered graphene wire, and an upper-layer contact connected to the upper surface side of the second multi-layered graphene wire.

Abstract: A conductive film of an embodiment includes: a fine catalytic metal particle as a junction and a graphene extending in a network form from the junction.

Abstract: According to one embodiment, a semiconductor device includes a catalyst underlying layer formed on a substrate including semiconductor elements formed thereon and processed in a wiring pattern, a catalyst metal layer that is formed on the catalyst underlying layer and whose width is narrower than that of the catalyst underlying layer, and a graphene layer growing with a sidewall of the catalyst metal layer set as a growth origin and formed to surround the catalyst metal layer.

Abstract: According to one embodiment, a graphene interconnection includes a first insulating film, a first catalyst film, and a first graphene layer. A first insulating film includes an interconnection trench. A first catalyst film is formed on the first insulating film on both side surfaces of the interconnection trench. A first graphene layer is formed on the first catalyst film on the both side surfaces of the interconnection trench, and including graphene sheets stacked in a direction perpendicularly to the both side surfaces.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate, an interlayer insulation film, a plug, a first mark, a second mark, and an upper wiring. The substrate has a device region and a mark formation region. The interlayer insulation film is formed on the substrate. The plug is made of a first metal material in the interlayer insulation film on the device region of the substrate. The first mark is made of the first metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark is made of a second metal material in the interlayer insulation film on the mark formation region of the substrate. The second mark has a concave on a surface thereof. The upper wiring is formed on the interlayer insulation film and is electrically connected to the plug.