Patents by Inventor Tatsuro Tsuneno
Tatsuro Tsuneno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9972884Abstract: A disclosed RFID tag includes a substrate; a chip bonded to the substrate with an adhesive, and including a first connection terminal on a first surface, the first surface being on a side bonded to the substrate; a first antenna wiring formed on the substrate, and electrically coupled to the first connection terminal; and an adhesive layer formed of the adhesive, and including a base portion and a filet portion, the base portion being in an area of the substrate opposed to the first surface of the chip, the filet portion being in an area of the substrate surrounding the chip. The first antenna wiring is electrically coupled to the first connection terminal via a plurality of paths at an outer edge of the filet portion of the adhesive layer.Type: GrantFiled: July 28, 2016Date of Patent: May 15, 2018Assignees: FUJITSU LIMITED, FUJITSU FRONTECH LIMITEDInventors: Takayoshi Matsumura, Yoshiyasu Sugimura, Hideo Miyazawa, Tatsuro Tsuneno
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Publication number: 20170062904Abstract: A disclosed RFID tag includes a substrate; a chip bonded to the substrate with an adhesive, and including a first connection terminal on a first surface, the first surface being on a side bonded to the substrate; a first antenna wiring formed on the substrate, and electrically coupled to the first connection terminal; and an adhesive layer formed of the adhesive, and including a base portion and a filet portion, the base portion being in an area of the substrate opposed to the first surface of the chip, the filet portion being in an area of the substrate surrounding the chip. The first antenna wiring is electrically coupled to the first connection terminal via a plurality of paths at an outer edge of the filet portion of the adhesive layer.Type: ApplicationFiled: July 28, 2016Publication date: March 2, 2017Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITEDInventors: Takayoshi Matsumura, Yoshiyasu SUGIMURA, Hideo MIYAZAWA, Tatsuro TSUNENO
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Patent number: 7595219Abstract: The present invention provides an IC chip mounting method for mounting two or more IC chips on a base, including: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into IC chips by dicing while leaving the tape; sequentially pressing the IC chips on the wafer against a first roller to allow the chips to be sucked onto the first roller; subsequently transferring the IC chips sucked onto the first roller to a second roller; and subsequently mounting the IC chips transferred to the second roller on the traveling base.Type: GrantFiled: January 4, 2006Date of Patent: September 29, 2009Assignees: Fujitsu Limited, Fujitsu Frontech LimitedInventors: Naoki Ishikawa, Tatsuro Tsuneno, Hidehiko Kira, Hiroshi Kobayashi
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Publication number: 20070181726Abstract: A series of RFID tags is reeled around a reel core formed by a core material and a stress absorbing material lapped around the core material to absorb a stress produced in reeling the series of RFID tags. In the series of RFID tags, a number of RFID tags each having an antenna and a circuit chip connected to the antenna and performing radio communication with the antenna are formed in a predetermined pitch on a long-belt-like and flexible base.Type: ApplicationFiled: October 18, 2006Publication date: August 9, 2007Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITEDInventors: Naoki Ishikawa, Tatsuro Tsuneno, Hidehiko Kira
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Patent number: 7214563Abstract: An IC chip mounting method which mounts two or more IC chips on a base, includes: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into IC chips by dicing while leaving the tape; positioning the wafer to face the base in such a direction that the mounting surface to be attached to the base faces the base; sequentially pressing the IC chips on the wafer against the base and temporarily fixing the IC chips while the base is being fed in a prescribed one-dimensional direction along the wafer and while the wafer is being moved two-dimensionally along the base; and fixing the IC chips temporarily fixed on the base on the base by heating and pressurizing in a batch manner.Type: GrantFiled: December 29, 2005Date of Patent: May 8, 2007Assignees: Fujitsu Limited, Fujitsu Frontech LimitedInventors: Naoki Ishikawa, Shunji Baba, Hidehiko Kira, Hiroshi Kobayashi, Shunichi Kikuchi, Tatsuro Tsuneno
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Publication number: 20070020800Abstract: An IC chip mounting method which mounts two or more IC chips on a base, includes: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into IC chips by dicing while leaving the tape; positioning the wafer to face the base in such a direction that the mounting surface to be attached to the base faces the base; sequentially pressing the IC chips on the wafer against the base and temporarily fixing the IC chips while the base is being fed in a prescribed one-dimensional direction along the wafer and while the wafer is being moved two-dimensionally along the base; and fixing the IC chips temporarily fixed on the base on the base by heating and pressurizing in a batch manner.Type: ApplicationFiled: December 29, 2005Publication date: January 25, 2007Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITEDInventors: Naoki Ishikawa, Shunji Baba, Hidehiko Kira, Hiroshi Kobayashi, Shunichi Kikuchi, Tatsuro Tsuneno
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Publication number: 20070020801Abstract: The present invention provides an IC chip mounting method for mounting two or more IC chips on a base, including: preparing a wafer by mounting a tape on a face thereof, which is the reverse of the wafer having a mounting surface to be attached to the base, and by dividing the wafer into IC chips by dicing while leaving the tape; sequentially pressing the IC chips on the wafer against a first roller to allow the chips to be sucked onto the first roller; subsequently transferring the IC chips sucked onto the first roller to a second roller; and subsequently mounting the IC chips transferred to the second roller on the traveling base.Type: ApplicationFiled: January 4, 2006Publication date: January 25, 2007Applicants: FUJITSU LIMITED, FUJITSU FRONTECH LIMITEDInventors: Naoki Ishikawa, Tatsuro Tsuneno, Hidehiko Kira, Hiroshi Kobayashi
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Patent number: 4530771Abstract: A lubricating oil composition containing esters constituted with glycerol, fatty acid and boric acid, which esters having carboxylic acid residue, glycerol residue and boric acid residue at a specific proportion.The proportion for the carboxylic acid residue and glycerol residue ranges 0-2.0 mols and 1.5-2.0 mols respectively per unit mol of a boric acid residue, and the glycerol residue is 1.2 mols or more based on 1 mol of the carboxylic acid residue.Lubricating oil additives according to the invention have almost no corrosion property in bearing portions, and do not form any solid film on themselves when allowed to stand in the air.Type: GrantFiled: July 26, 1983Date of Patent: July 23, 1985Assignee: Karonite Chemical Co., Ltd.Inventors: Takaharu Nakano, Akihiro Mochizuki, Morikuni Nakazato, Tatsuro Tsuneno
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Patent number: 4515725Abstract: Preparation of boric esters of glycerol fatty acid esters which comprises reacting triglycerides such as natural oils and fats with glycerol and boric acid in specific ratios.3 mols of boric acid, 1 to 2 mols of at least one long-chain fatty acid triglyceride, and 4 to 5 mols of glycerol are interacted under neutral or acidic conditions at a temperature of 240.degree.-280.degree. C.According to the invention, boric esters can be obtained substantially in quantitative and good yield because of a small loss of reaction.Type: GrantFiled: July 26, 1983Date of Patent: May 7, 1985Assignee: Kao CorporationInventors: Tatsuro Tsuneno, Masaaki Takaku