Patents by Inventor Tatsuya Iwai

Tatsuya Iwai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111181
    Abstract: An object of the present invention is to provide an optical switch element, an optical switch device, an optical communication system, and an optical computer capable of operating even in a temperature range higher than the NĂ©el temperature. An optical switch element (10) according to the present invention includes a substance including a plurality of transition metal elements having electrons in d-orbitals, and a plurality of anions arranged around each of the plurality of transition metal elements, in which the plurality of transition metal elements are arranged in a lattice form, t2g-orbitals into which the d-orbitals of each of the plurality of transition metal elements are split are connected annularly, and in a state in which the substance does not have a long-range magnetic order, the polarization of signal light (L1) is rotated when control light (C1) is applied.
    Type: Application
    Filed: December 2, 2021
    Publication date: April 4, 2024
    Applicants: TOHOKU UNIVERSITY, CHUO UNIVERSITY
    Inventors: Shinichiro IWAI, Yohei KAWAKAMI, Tatsuya AMANO, Kenya OHGUSHI, Kenji YONEMITSU
  • Publication number: 20240080254
    Abstract: There are provided a signal generator capable of flexibly increasing the number of taps while realizing high-speed emphasis switching and an emphasis switching method using the signal generator. A signal generator includes: an emphasis addition circuit including at least one finite impulse response (FIR) filter unit that generates an emphasis waveform pattern by adding an emphasis to a pattern of a pulse amplitude modulation (PAM) signal including multi-values which are two or more values; and a tap value setting unit that switches M tap values C(0), C(?1), . . . , and C(1?M) and sets the M tap values C(0), C(?1), . . . , and C(1?M) to each FIR filter unit according to an emphasis switching request from a DUT 100. The FIR filter unit is configured on an FPGA or an ASIC.
    Type: Application
    Filed: June 15, 2023
    Publication date: March 7, 2024
    Inventor: Tatsuya IWAI
  • Publication number: 20240039688
    Abstract: A signal generation device includes m transceivers, a usage amount determination unit that executes a usage amount determination process that determines the usage amount of the FIFO of each transceiver, and a phase adjustment unit that adjusts the phase of the read clock signal for the FIFO. The signal generation device performs the second usage amount determination process on the condition that the count that the usage amount of the FIFO of each transceiver is determined to be less than the usage amount threshold by the first usage amount determination process consecutively reaches the first determination count, and terminates the adjustment of the phase of the read clock signal on the condition that the count that the usage amount of the FIFO of each transceiver is determined by the second usage amount determination process to be greater than the usage amount threshold consecutively reaches the second determination count.
    Type: Application
    Filed: June 13, 2023
    Publication date: February 1, 2024
    Inventors: Hironori YOSHIOKA, Tatsuya IWAI
  • Patent number: 11626944
    Abstract: There are provided a data comparison unit that detects an FEC symbol error of a signal under test output from a DUT in accordance with an input of a jitter signal, an error counting unit that counts the number of detected FEC symbol errors for each codeword for each phase modulation amount, a codeword classification unit that classifies a plurality of codewords included in the signal under test into a plurality of groups based on the counted number of FEC symbol errors, a codeword number counting unit that counts the number of codewords in each group for each phase modulation amount, and a display control unit that controls a display of a first graph having a horizontal axis as the phase modulation amount and a vertical axis as a ratio of the number of codewords in each group, on a display screen.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: April 11, 2023
    Assignee: ANRITSU CORPORATION
    Inventor: Tatsuya Iwai
  • Patent number: 11588479
    Abstract: Provided are a spread spectrum clock generator and a spread spectrum clock generation method, a pulse pattern generator and a pulse pattern generation method, and an error rate measuring device and an error rate measuring method capable of improving usability when adjusting a waveform of a modulation signal during training. A setting screen 60 includes a 0-th frequency shift input unit 71 for arbitrarily setting a frequency shift of a waveform of a modulation signal in a plurality of time sections, a first frequency shift input unit 72, a second frequency shift input unit 73, a third frequency shift input unit 74, and a modulation selection unit 67 for switching a waveform pattern of the modulation signal from a first pattern to a second pattern.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: February 21, 2023
    Assignee: ANRITSU CORPORATION
    Inventor: Tatsuya Iwai
  • Publication number: 20220337359
    Abstract: There are provided a data comparison unit that detects an FEC symbol error of a signal under test output from a DUT in accordance with an input of a jitter signal, an error counting unit that counts the number of detected FEC symbol errors for each codeword for each phase modulation amount, a codeword classification unit that classifies a plurality of codewords included in the signal under test into a plurality of groups based on the counted number of FEC symbol errors, a codeword number counting unit that counts the number of codewords in each group for each phase modulation amount, and a display control unit that controls a display of a first graph having a horizontal axis as the phase modulation amount and a vertical axis as a ratio of the number of codewords in each group, on a display screen.
    Type: Application
    Filed: February 23, 2022
    Publication date: October 20, 2022
    Inventor: Tatsuya IWAI
  • Publication number: 20220255542
    Abstract: Provided are a spread spectrum clock generator and a spread spectrum clock generation method, a pulse pattern generator and a pulse pattern generation method, and an error rate measuring device and an error rate measuring method capable of improving usability when adjusting a waveform of a modulation signal during training. A setting screen 60 includes a 0-th frequency shift input unit 71 for arbitrarily setting a frequency shift of a waveform of a modulation signal in a plurality of time sections, a first frequency shift input unit 72, a second frequency shift input unit 73, a third frequency shift input unit 74, and a modulation selection unit 67 for switching a waveform pattern of the modulation signal from a first pattern to a second pattern.
    Type: Application
    Filed: December 15, 2021
    Publication date: August 11, 2022
    Inventor: Tatsuya IWAI
  • Patent number: 11336501
    Abstract: [Task] There is provided a signal generation apparatus and a signal generation method capable of performing mutual switching between a PAM N signal having n values and a PAM M signal having m values (m<n) without generating a noise or an overvoltage. [Means for Resolution] There are provided a PAM N generation circuit 41 that generates a PAM N signal of n values, a PAM M generation circuit 42 that generates a PAM M signal of m values (m<n) having a maximum voltage level equal to a maximum voltage level of the PAM N signal generated by the PAM N generation circuit 41, and a selector 43 that outputs any one of the PAM N signal generated by the PAM N generation circuit 41 and the PAM M signal generated by the PAM M generation circuit 42.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: May 17, 2022
    Assignee: ANRITSU CORPORATION
    Inventors: Tatsuya Iwai, Tomoaki Kabasawa
  • Patent number: 11283481
    Abstract: Provided are a spread spectrum clock generator and a spread spectrum clock generation method, a pulse pattern generator and a pulse pattern generation method, and an error rate measuring device and an error rate measuring method capable of performing SSC modulation of any frequency shift according to a standard. Included are a reference signal generator 10 that generates a reference signal, a modulation waveform generator 20 that generates a modulation waveform, a modulation unit 30 that frequency-modulates the reference signal with the modulation waveform to generate an SSC modulated signal, and a modulation control unit 42a capable of arbitrarily controlling the frequency shift of the modulation waveform and a slope of the frequency shift in any time section.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: March 22, 2022
    Assignee: ANRITSU CORPORATION
    Inventor: Tatsuya Iwai
  • Publication number: 20220021412
    Abstract: Provided are a spread spectrum clock generator and a spread spectrum clock generation method, a pulse pattern generator and a pulse pattern generation method, and an error rate measuring device and an error rate measuring method capable of performing SSC modulation of any frequency shift according to a standard. Included are a reference signal generator 10 that generates a reference signal, a modulation waveform generator 20 that generates a modulation waveform, a modulation unit 30 that frequency-modulates the reference signal with the modulation waveform to generate an SSC modulated signal, and a modulation control unit 42a capable of arbitrarily controlling the frequency shift of the modulation waveform and a slope of the frequency shift in any time section.
    Type: Application
    Filed: May 27, 2021
    Publication date: January 20, 2022
    Inventor: Tatsuya IWAI
  • Publication number: 20210273840
    Abstract: [Task] There is provided a signal generation apparatus and a signal generation method capable of performing mutual switching between a PAM N signal having n values and a PAM M signal having m values (m<n) without generating a noise or an overvoltage. [Means for Resolution] There are provided a PAM N generation circuit 41 that generates a PAM N signal of n values, a PAM M generation circuit 42 that generates a PAM M signal of m values (m<n) having a maximum voltage level equal to a maximum voltage level of the PAM N signal generated by the PAM N generation circuit 41, and a selector 43 that outputs any one of the PAM N signal generated by the PAM N generation circuit 41 and the PAM M signal generated by the PAM M generation circuit 42.
    Type: Application
    Filed: December 15, 2020
    Publication date: September 2, 2021
    Inventors: Tatsuya IWAI, Tomoaki KABASAWA
  • Patent number: 10587374
    Abstract: A signal generator includes inverse characteristic calculation means for calculating an inverse characteristic of a transfer function from an inverse characteristic of a frequency characteristic of a signal based on the transmission standard, inverse Fourier transform means for calculating impulse responses of a plurality of points by performing inverse Fourier transform on the inverse characteristic of the transfer function, impulse response cutout means for cutting out the points for a predetermined number of taps from the impulse response, frequency characteristic calculation means for calculating a frequency characteristic based on values of the points for the number of taps cut out from the impulse response, and display control means for displaying on a display screen, the frequency characteristic calculated by the frequency characteristic calculation means and an ideal frequency characteristic read from an S parameter file of a device under test.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 10, 2020
    Assignee: ANRITSU CORPORATION
    Inventors: Tatsuya Iwai, Hiroyuki Onuma
  • Publication number: 20200036486
    Abstract: A signal generator includes inverse characteristic calculation means for calculating an inverse characteristic of a transfer function from an inverse characteristic of a frequency characteristic of a signal based on the transmission standard, inverse Fourier transform means for calculating impulse responses of a plurality of points by performing inverse Fourier transform on the inverse characteristic of the transfer function, impulse response cutout means for cutting out the points for a predetermined number of taps from the impulse response, frequency characteristic calculation means for calculating a frequency characteristic based on values of the points for the number of taps cut out from the impulse response, and display control means for displaying on a display screen, the frequency characteristic calculated by the frequency characteristic calculation means and an ideal frequency characteristic read from an S parameter file of a device under test.
    Type: Application
    Filed: April 25, 2019
    Publication date: January 30, 2020
    Inventors: Tatsuya IWAI, Hiroyuki ONUMA
  • Patent number: 10536310
    Abstract: In a signal generating device 2, first signal generation means 12 for generating a most significant bit signal stream MSB, second signal generation means 13 for generating a least significant bit signal stream LSB, a mask generation means 14 for defining a bit that allows error insertion and a bit that prohibits error insertion with different pieces of bit information, and generating a mask pattern of each of the most significant bit signal stream MSB and the least significant bit signal stream LSB, based on symbol transition information indicating a transition destination of four PAM4 symbols of a PAM4 signal; and error insertion means 15 for inserting an error, based on bit information of the mask pattern corresponding to each bit of the most significant bit signal stream and the least significant bit signal stream designated according to a symbol error rate.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: January 14, 2020
    Assignee: ANRITSU CORPORATION
    Inventor: Tatsuya Iwai
  • Publication number: 20190363917
    Abstract: In a signal generating device 2, first signal generation means 12 for generating a most significant bit signal stream MSB, second signal generation means 13 for generating a least significant bit signal stream LSB, a mask generation means 14 for defining a bit that allows error insertion and a bit that prohibits error insertion with different pieces of bit information, and generating a mask pattern of each of the most significant bit signal stream MSB and the least significant bit signal stream LSB, based on symbol transition information indicating a transition destination of four PAM4 symbols of a PAM4 signal; and error insertion means 15 for inserting an error, based on bit information of the mask pattern corresponding to each bit of the most significant bit signal stream and the least significant bit signal stream designated according to a symbol error rate.
    Type: Application
    Filed: April 2, 2019
    Publication date: November 28, 2019
    Inventor: Tatsuya IWAI
  • Patent number: D868311
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: November 26, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hideaki Iida, Tatsuya Iwai, Takuya Ishibashi
  • Patent number: D875607
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: February 18, 2020
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hideaki Iida, Nobuyuki Tomatsu, Tatsuya Iwai, Shunsuke Sudo
  • Patent number: D1003207
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: October 31, 2023
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Tatsuya Iwai
  • Patent number: D1014351
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 13, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Masaki Okue, Tatsuya Iwai
  • Patent number: D1021716
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: April 9, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tatsuya Iwai, Shigetoshi Kozai