Patents by Inventor Tatsuya Kato

Tatsuya Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10134750
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 20, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tatsuya Kato, Wataru Sakamoto, Fumitaka Arai
  • Publication number: 20180323204
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Application
    Filed: June 26, 2018
    Publication date: November 8, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Mikiko MORI, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Publication number: 20180301461
    Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.
    Type: Application
    Filed: June 19, 2018
    Publication date: October 18, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Atsushi Murakoshi, Fumitaka Arai
  • Patent number: 10103155
    Abstract: A semiconductor memory device according to an embodiment, includes a first semiconductor member, a second semiconductor member, an insulating member, a plurality of electrode films, a first electrode, and a second electrode. The first semiconductor member and the second semiconductor member are separated in a first direction and extending in a second direction. The second direction crosses the first direction. The insulating member is provided between the first semiconductor member and the second semiconductor member. The plurality of electrode films are arranged to be separated from each other along the second direction. Each of the electrode films surrounds the first semiconductor member, the second semiconductor member, and the insulating member when viewed from the second direction. The first electrode is provided between the first semiconductor member and the electrode film. The second electrode is provided between the second semiconductor member and the electrode film.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kohei Sakaike, Toshiyuki Iwamoto, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Satoshi Nagashima, Koichi Sakata, Yuta Watanabe
  • Publication number: 20180269218
    Abstract: A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.
    Type: Application
    Filed: September 14, 2017
    Publication date: September 20, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya KATO, Fumitaka Arai, Kohei Sakaike, Satoshi Nagashima
  • Patent number: 10043815
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: August 7, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima
  • Patent number: 10032935
    Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 24, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masaaki Higuchi, Masao Shingu, Tatsuya Kato, Takeshi Murata, Makoto Fujiwara, Masaki Kondo, Muneyuki Tsuda, Takashi Kurusu
  • Patent number: 10020315
    Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: July 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Atsushi Murakoshi, Fumitaka Arai
  • Patent number: 9984754
    Abstract: According to an embodiment, an operation method for a memory device which has a first memory element and a second memory element respectively provided on both sides of a semiconductor member includes applying a first potential on the second word line to write a second data to the second memory and applying a second potential on the first word line to write the first data to the first memory. The first potential increases by a first step voltage and the second potential increases by a second step voltage.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 29, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Wataru Sakamoto, Fumitaka Arai, Tatsuya Kato
  • Patent number: 9966381
    Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 8, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Fumitaka Arai, Tatsuya Kato, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi
  • Publication number: 20180083022
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, semiconductor pillars, first electrode films, a second electrode film, a first insulating film, a second insulating film, and a contact. The semiconductor pillars are provided on the substrate, extend in a first direction crossing an upper surface of the substrate, and are arranged along second and third directions being parallel to the upper surface and crossing each other. The first electrode films extend in the third direction. The second electrode film is provided between the semiconductor pillars and the first electrode films. The first insulating film is provided between the semiconductor pillars and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode films. The contact is provided at a position on the third direction of the semiconductor pillars and is connected to the first electrode films.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya KATO, Wataru SAKAMOTO, Fumitaka ARAI
  • Publication number: 20180006051
    Abstract: A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Satoshi NAGASHIMA, Tatsuya KATO
  • Publication number: 20180006050
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.
    Type: Application
    Filed: September 14, 2017
    Publication date: January 4, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Yuta Watanabe, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Wataru Sakamoto, Tatsuya Kato
  • Publication number: 20170373082
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, a second insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, and a conductive film provided between the second electrode and the second insulating film, the conductive film not contacting the first insulating film.
    Type: Application
    Filed: August 22, 2017
    Publication date: December 28, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Katsuyuki SEKINE, Tatsuya KATO, Fumitaka ARAI, Toshiyuki IWAMOTO, Yuta WATANABE, Wataru SAKAMOTO, Hiroshi ITOKAWA, Akio KANEKO
  • Patent number: 9847342
    Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: December 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Nagashima, Katsumi Yamamoto, Kohei Sakaike, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Atsushi Murakoshi, Shunichi Takeuchi, Katsuyuki Sekine
  • Publication number: 20170352735
    Abstract: A semiconductor memory device according to an embodiment, includes a pair of first electrodes, a semiconductor pillar, an inter-pillar insulating member, a first insulating film, a second electrode, and a second insulating film. The pair of first electrodes are separated from each other, and extend in a first direction. The semiconductor pillar and the inter-pillar insulating member are arranged alternately along the first direction between the pair of first electrodes. The semiconductor pillar and the inter-pillar insulating member extend in a second direction crossing the first direction. The first insulating film is provided at a periphery of the semiconductor pillar. The second electrode is provided between the first insulating film and each electrode of the pair of first electrodes. The second electrode is not provided between the semiconductor pillar and the inter-pillar insulating member. The second insulating film is provided between the second electrode and the first electrode.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuke Iwamoto, Yuta Watanabe, Wataru Sakamoto
  • Publication number: 20170350715
    Abstract: Route search systems, methods, and programs search for a recommended route using a cost value of a link or a node that constitutes a route. The systems, methods, and programs calculate the cost value of the link or the node on the basis of calculation material information that serves as a material for calculating the cost value, and specify a reliability degree of the calculated cost value of the link or the node on the basis of a number of pieces of the calculation material information used to calculate the cost value of the link or the node. The systems, methods, and programs correct the cost value of the link or the node, the reliability degree of which has been specified, on the basis of the specified reliability degree, and search for the recommended route using the corrected cost value.
    Type: Application
    Filed: August 31, 2015
    Publication date: December 7, 2017
    Applicants: AISIN AW CO., LTD., AISIN AW CO., LTD., TOYOTA JIDOSHA KABUSHIKI KAISHA, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daisuke TANIZAKI, Toyoji HIYOKAWA, Tatsuya KATO, Motohiro NAKAMURA, Kazunori WATANABE, Hiroyuki TASHIRO, Kei HIROO
  • Publication number: 20170352672
    Abstract: A semiconductor memory device according to an embodiment includes first and second semiconductor pillars extending in a first direction and being arranged along a second direction, first and second interconnects extending in a third direction and being provided between the first semiconductor pillar and the second semiconductor pillar, a first electrode provided between the first semiconductor pillar and the first interconnect, a second electrode provided between the second semiconductor pillar and the second interconnect, third and fourth interconnects extending in the second direction, a first contact contacting the first semiconductor pillar and being connected to the third interconnect, and a second contact contacting the second semiconductor pillar and being connected to the fourth interconnect. The third and fourth interconnects each pass through both a region directly above the first semiconductor pillar and a region directly above the second semiconductor pillar.
    Type: Application
    Filed: August 25, 2017
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Wataru SAKAMOTO, Tatsuya KATO, Yuta WATANABE, Katsuyuki SEKINE, Toshiyuki IWAMOTO, Fumitaka ARAI
  • Publication number: 20170352671
    Abstract: A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the first electrode and the second electrode and on two first-direction sides of the first electrode, a second insulating film provided between the second electrode and the first insulating film and on two first-direction sides of the second electrode, a third insulating film provided between the second electrode and the semiconductor pillar, and a conductive film provided inside a region interposed between the first insulating film and the second insulating film.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Katsuyuki Sekine, Toshiyuki Iwamoto, Yuta Watanabe, Wataru Sakamoto, Hiroshi Itokawa
  • Publication number: 20170345837
    Abstract: A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.
    Type: Application
    Filed: August 10, 2017
    Publication date: November 30, 2017
    Applicant: Toshiba Memory Corporation
    Inventors: Mikiko Mori, Ryota Suzuki, Tatsuya Kato, Wataru Sakamoto, Fumie Kikushima