Patents by Inventor Tatsuya Kawamata

Tatsuya Kawamata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8710619
    Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Kawamata, Atsushi Tachigami, Kazuya Horie, Tatsuya Shiromoto, Tetsuya Nitta, Hironori Shimizu
  • Publication number: 20120049318
    Abstract: To provide, in a semiconductor device formed on an SOI substrate and having a semiconductor layer of the SOI substrate surrounded, at the periphery of the element region thereof, with element isolation, a technology capable of preventing reliability deterioration attributed to the element isolation. Appearance of a hollow, which is formed upon filling of a deep trench with an insulating film, from the upper surface of the insulating film can be prevented by setting the trench width of the upper portion of the deep trench configuring trench isolation at less than 1.2 ?m. Reduction in the breakdown voltage between adjacent element regions which may presumably occur due to a decrease in the trench width of the upper portion of the deep trench can be prevented by forming, on the upper portion of the deep trench, an LOCOS insulating film coupled to the insulating film filled in the deep trench.
    Type: Application
    Filed: August 11, 2011
    Publication date: March 1, 2012
    Inventors: Tatsuya Kawamata, Atsushi Tachigami, Kazuya Horie, Tatsuya Shiromoto, Tetsuya Nitta, Hironori Shimizu
  • Publication number: 20050242377
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOGOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 3, 2005
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6917076
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: July 12, 2005
    Assignee: United Microelectronics Corporation
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Publication number: 20040021160
    Abstract: A semiconductor device and a method for manufacturing the same and method for deleting information in use of the semiconductor device, in which field shield isolation or a trench type isolation between elements is used with suppression of penetration of field oxide into element active region of the device, that is, a defect involved in conventional LOCOS type process, are disclosed. A non-LOCOS insulating device isolation block is formed in a semiconductor substrate. The non-LOCOS insulating device isolation block uses a field shield element isolation structure or trench type element isolation structure.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 5, 2004
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6657229
    Abstract: A semiconductor device has field shield isolation or trench type isolation between elements which suppresses penetration of field oxide into an element active region of the device. A common gate is located between two MOS transistors, which may be of opposite conductivity type. After gate electrode wiring layers are formed in a field region and an active region to the same level, a pad polysilicon film formed on the entire surface to cover the patterns of these gate electrode wiring layers, which are in separated patterns.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: December 2, 2003
    Assignee: United Microelectronics Corporation
    Inventors: Kohei Eguchi, Yuichi Egawa, Shoichi Iwasa, Hideki Fujikake, Wataru Yokozeki, Tatsuya Kawamata
  • Patent number: 6468887
    Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: October 22, 2002
    Assignee: Nippon Steel Corporation
    Inventors: Shoichi Iwasa, Tatsuya Kawamata
  • Publication number: 20020125536
    Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.
    Type: Application
    Filed: July 18, 2001
    Publication date: September 12, 2002
    Applicant: Nippon Steel Corporation
    Inventors: Shoichi Iwasa, Tatsuya Kawamata
  • Patent number: 6288431
    Abstract: In a semiconductor device of this invention, a pillar projection serving as a very thin active region is formed on the surface of a p-type silicon semiconductor substrate. A gate electrode 21 is formed to cover a central portion of the pillar projection. A pair of impurity diffusion layers 22 are formed on the pillar projection on the two sides of the gate electrode. An element isolation insulating film 23 is formed to sandwich and bury the side surfaces of the pillar projection. This semiconductor device has high performance equivalent to that of an SOI structure. The semiconductor device of this invention has three channels corresponding to a pair of a source and a drain, is selectively formed on the same semiconductor substrate as a common bulk transistor, and has a very fine structure and high drivability.
    Type: Grant
    Filed: April 3, 1998
    Date of Patent: September 11, 2001
    Assignee: Nippon Steel Corporation
    Inventors: Shoichi Iwasa, Tatsuya Kawamata