Patents by Inventor Tatsuya Ohguro

Tatsuya Ohguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11038721
    Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: June 15, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya Ohguro, Tatsuhiro Oda, Kenichi Ootsuka
  • Patent number: 10998437
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·?m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pr
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 4, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya Ohguro, Tatsuya Nishiwaki, Hideharu Kojima, Yoshiharu Takada, Kikuo Aida, Kentaro Ichinoseki, Kohei Oasa, Shingo Sato
  • Publication number: 20210083908
    Abstract: According to one embodiment, a digital isolator includes a first metal portion, a first insulating portion, a second metal portion, a third metal portion, and a first layer. The first insulating portion is provided on the first metal portion. The second metal portion is provided on the first insulating portion. The third metal portion includes first, second, and third portions. The first portion is provided around the first metal portion in a direction perpendicular to a first direction. The second portion is provided on a portion of the first portion with a first conductive layer interposed. The third portion is provided on the second portion and provided around the second metal portion in the perpendicular direction. The first layer contacts the first conductive layer and an other portion of the first portion and is provided around a bottom portion of the second portion.
    Type: Application
    Filed: March 11, 2020
    Publication date: March 18, 2021
    Inventors: Tatsuya Ohguro, Tatsuhiro Oda, Kenichi Ootsuka
  • Publication number: 20200152785
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate having a first plane and a second plane, a semiconductor element provided in the semiconductor substrate, the semiconductor element including a gate insulating film provided in the first plane, a first electrode provided on the first plane, a second electrode provided on the first electrode, the second electrode including a first metal material, the second electrode having a film thickness of (65 [g·?m·cm?3])/(density of the first metal material [g·cm?3]) or more, a first solder portion provided on the second electrode, a third electrode provided on the first solder portion, a fourth electrode provided on the first plane, a fifth electrode provided on the fourth electrode, the fifth electrode including a second metal material, the fifth electrode having a film thickness of (65 [g·m·cm?3])/(density of the second metal material [g·cm?3]) or more, a second solder portion provided on the fifth electrode, and a sixth electrode pro
    Type: Application
    Filed: August 5, 2019
    Publication date: May 14, 2020
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tatsuya OHGURO, Tatsuya NISHIWAKI, Hideharu KOJIMA, Yoshiharu TAKADA, Kikuo AIDA, Kentaro ICHINOSEKI, Kohei OASA, Shingo SATO
  • Patent number: 10246324
    Abstract: According to one embodiment, a strain and pressure sensing device includes a semiconductor circuit unit and a sensing unit. The semiconductor circuit unit includes a semiconductor substrate and a transistor. The transistor is provided on a semiconductor substrate. The sensing unit is provided on the semiconductor circuit unit, and has space and non-space portions. The non-space portion is juxtaposed with the space portion. The sensing unit further includes a movable beam, a strain sensing element unit, and first and second buried interconnects. The movable beam has fixed and movable portions, and includes first and second interconnect layers. The fixed portion is fixed to the non-space portion. The movable portion is separated from the transistor and extends from the fixed portion into the space portion. The strain sensing element unit is fixed to the movable portion. The first and second buried interconnects are provided in the non-space portion.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 2, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki Fukuzawa, Tatsuya Ohguro, Akihiro Kojima, Yoshiaki Sugizaki, Mariko Takayanagi, Yoshihiko Fuji, Akio Hori, Michiko Hara
  • Publication number: 20180076287
    Abstract: A semiconductor device includes: a nitride semiconductor layer; a silicon substrate including a first region of a first conductivity type, a second region of a second conductivity type provided between the first region and the nitride semiconductor layer, a third region of the first conductivity type provided between the second region and the nitride semiconductor layer, a fourth region of the second conductivity type provided between the third region and the nitride semiconductor layer, a fifth region of the first conductivity type provided between the fourth region and the nitride semiconductor layer, and a sixth region of the second conductivity type provided between the fifth region and the nitride semiconductor layer; a first electrode, the nitride semiconductor layer being located between the silicon substrate and the first electrode; and a second electrode that is spaced from the first electrode and located between the silicon substrate and the second electrode.
    Type: Application
    Filed: March 3, 2017
    Publication date: March 15, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya OHGURO
  • Publication number: 20180009656
    Abstract: According to one embodiment, a strain and pressure sensing device includes a semiconductor circuit unit and a sensing unit. The semiconductor circuit unit includes a semiconductor substrate and a transistor. The transistor is provided on a semiconductor substrate. The sensing unit is provided on the semiconductor circuit unit, and has space and non-space portions. The non-space portion is juxtaposed with the space portion. The sensing unit further includes a movable beam, a strain sensing element unit, and first and second buried interconnects. The movable beam has fixed and movable portions, and includes first and second interconnect layers. The fixed portion is fixed to the non-space portion. The movable portion is separated from the transistor and extends from the fixed portion into the space portion. The strain sensing element unit is fixed to the movable portion. The first and second buried interconnects are provided in the non-space portion.
    Type: Application
    Filed: September 12, 2017
    Publication date: January 11, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideaki FUKUZAWA, Tatsuya OHGURO, Akihiro KOJIMA, Yoshiaki SUGIZAKI, Mariko TAKAYANAGI, Yoshihiko FUJI, Akio HORI, Michiko HARA
  • Patent number: 9831290
    Abstract: According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: November 28, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shuichi Toriyama, Kenichi Murooka, Shintaro Nakano, Tatsuya Ohguro
  • Patent number: 9790087
    Abstract: According to one embodiment, a strain and pressure sensing device includes a semiconductor circuit unit and a sensing unit. The semiconductor circuit unit includes a semiconductor substrate and a transistor. The transistor is provided on a semiconductor substrate. The sensing unit is provided on the semiconductor circuit unit, and has space and non-space portions. The non-space portion is juxtaposed with the space portion. The sensing unit further includes a movable beam, a strain sensing element unit, and first and second buried interconnects. The movable beam has fixed and movable portions, and includes first and second interconnect layers. The fixed portion is fixed to the non-space portion. The movable portion is separated from the transistor and extends from the fixed portion into the space portion. The strain sensing element unit is fixed to the movable portion. The first and second buried interconnects are provided in the non-space portion.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 17, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Fukuzawa, Tatsuya Ohguro, Akihiro Kojima, Yoshiaki Sugizaki, Mariko Takayanagi, Yoshihiko Fuji, Akio Hori, Michiko Hara
  • Publication number: 20170263681
    Abstract: According to one embodiment, a semiconductor memory device includes first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction, a first semiconductor layer extending in the second direction and including a material having one of a first conductivity type and a second conductivity type, a first insulation layer disposed inside the first semiconductor layer, a second conductive layer disposed inside the first insulation layer, and a variable resistance layer disposed between the first conductive layers and the first semiconductor layer.
    Type: Application
    Filed: March 10, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shuichi TORIYAMA, Kenichi MUROOKA, Shintaro Nakano, Tatsuya OHGURO
  • Publication number: 20160380115
    Abstract: A thin film transistor includes semiconductor layer, source electrode, and drain electrode. The semiconductor layer includes first to fifth regions. The third region is provided between the first and second regions. The first region is disposed between the fourth and third regions. The second region is disposed between the fifth and third regions. The semiconductor layer includes an oxide. The source electrode is connected to the first region. The drain electrode is connected to the second region. First thickness of the first region along a second direction is thinner than third thickness along the second direction of each of the third to fifth regions. The second direction crosses a first direction and connects the first region and the source electrode. The first direction connects the first and second regions. Second thickness of the second region along the second direction is thinner than the third thickness.
    Type: Application
    Filed: September 7, 2016
    Publication date: December 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shintaro NAKANO, Yuya MAEDA, Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Kazuya FUKASE, Nobuki KANREI
  • Publication number: 20160284746
    Abstract: According to one embodiment, a solid-state imaging device includes a plurality of photoelectric conversion elements, a field effect transistor, a trench, and a P-type impurity diffusion region. The plurality of photoelectric conversion elements is two-dimensionally arranged in a semiconductor layer. The field effect transistor includes N-type source and drain on a surface side of the semiconductor layer. The trench penetrates through a surface and a rear surface of the semiconductor layer and surrounds each of the photoelectric conversion elements. The width of the trench is enlarged from the surface of the semiconductor layer toward a position at a predetermined depth, and is not enlarged at a position deeper than the position at the predetermined depth. The P-type impurity diffusion region is arranged in a side surface of the trench.
    Type: Application
    Filed: June 19, 2015
    Publication date: September 29, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya FUKASE, Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Takahisa KANEMURA
  • Patent number: 9318615
    Abstract: A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a source electrode and a drain electrode. The first dielectric film is placed above the gate electrode. The oxide semiconductor film is placed above the first dielectric film. The oxide semiconductor film is formed to have a film thickness in a first contact region in contact with the source electrode and a second contact region in contact with the drain electrode larger than a film thickness in a channel region of the oxide semiconductor film so that a film portion of the first contact region projects toward the source electrode side and a film portion of the second contact region projects toward the drain electrode side.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 19, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tatsuya Ohguro, Hisayo Momose, Tetsu Morooka, Kazuya Fukase
  • Publication number: 20160093742
    Abstract: A semiconductor device according to an embodiment, includes a gate electrode, a first dielectric film, a first oxide semiconductor film, a second dielectric film, a source electrode, a source wire, a drain electrode, and a drain wire. The source wire is arranged on the second dielectric film, and connected to the source electrode. The drain wire is arranged on the second dielectric film, and connected to the drain electrode. At least one of the source wire and the drain wire includes a fringe portion sticking out above a channel region. A barrier film that suppresses intrusion of hydrogen is arranged being in contact with at least one of an upper surface and a lower surface of the fringe portion. A region where the barrier film is not formed is included above the channel region.
    Type: Application
    Filed: March 19, 2015
    Publication date: March 31, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hisayo MOMOSE, Tatsuya OHGURO, Tetsu MOROOKA, Kazuya FUKASE, Shintaro NAKANO, Yuya MAEDA, Shuichi TORIYAMA, Nobuki KANREI
  • Publication number: 20160043130
    Abstract: According to one embodiment, a solid-state imaging device includes an element isolation film, a photoelectric conversion element, and a transfer transistor. The element isolation film is embedded in a first trench penetrating a semiconductor substrate from a first main surface to a second main surface. The photoelectric conversion element is embedded in a pixel region isolated by the element isolation film, and includes a P-type region formed on the second main surface side along the first trench and an N-type region formed at a region surrounded by the P-type region. The transfer transistor is formed at the first main surface and configured to transfer a charge of the photoelectric conversion element. A part of the element isolation film on the first main surface side is formed of an active region.
    Type: Application
    Filed: December 2, 2014
    Publication date: February 11, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tatsuya OHGURO
  • Patent number: 9224850
    Abstract: In one embodiment, a first main terminal region of a first conductivity type and a second main terminal region of a second conductivity type, which is an opposite conductivity type of the first conductivity type, formed in the semiconductor substrate so as to sandwich a gate electrode, a diffusion layer of the second conductivity type coming in contact with the first and second element isolation insulator films and having an upper surface in a position deeper than lower surfaces of the first and second main terminal regions, a first well region of the first conductivity type formed between the first main terminal region and the diffusion layer, and a second well region of the first conductivity type formed between the second main terminal region and the diffusion layer. The second well region has a impurity concentration higher than that of the first well region.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: December 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masakazu Goto, Shigeru Kawanaka, Akira Hokazono, Tatsuya Ohguro, Yoshiyuki Kondo
  • Patent number: 9196698
    Abstract: A semiconductor device according to an embodiment, includes a source electrode, a drain electrode arranged apart from the source electrode, an oxide semiconductor film, a gate dielectric film, and a gate electrode. The oxide semiconductor film is arranged below the source electrode and the drain electrode to connect the source electrode and the drain electrode. The gate dielectric film is formed below the oxide semiconductor film such that a thickness below at least one of the source electrode and the drain electrode is made thinner than a thickness below a channel region of the oxide semiconductor film between the source electrode and the drain electrode. The gate electrode is arranged below the gate dielectric film and formed in a position where one of portions of the gate electrode overlaps with the source electrode and another one of the portions of the gate electrode overlaps with the drain electrode.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 24, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Fukase, Tatsuya Ohguro, Hisayo Momose, Tetsu Morooka
  • Publication number: 20150249156
    Abstract: A semiconductor device according to an embodiment includes a gate electrode, a first dielectric film, an oxide semiconductor film, a second dielectric film, a source electrode and a drain electrode. The first dielectric film is placed above the gate electrode. The oxide semiconductor film is placed above the first dielectric film. The oxide semiconductor film is formed to have a film thickness in a first contact region in contact with the source electrode and a second contact region in contact with the drain electrode larger than a film thickness in a channel region of the oxide semiconductor film so that a film portion of the first contact region projects toward the source electrode side and a film portion of the second contact region projects toward the drain electrode side.
    Type: Application
    Filed: June 27, 2014
    Publication date: September 3, 2015
    Inventors: Tatsuya OHGURO, Hisayo MOMOSE, Tetsu MOROOKA, Kazuya FUKASE
  • Publication number: 20150244958
    Abstract: According to one embodiment, there is provided a solid-state imaging device including a plurality of pixels. Each of the plurality of pixels includes a first photoelectric conversion unit, a second photoelectric conversion unit, a multilayer interference filter, and a reflective unit. The first photoelectric conversion unit includes a photoelectric conversion film photoelectrically converting first color light. In the multilayer interference filter, first and second layers having different refractive indexes are alternately laminated. The multilayer interference filter selectively guides at least second color light of light having passed through the first photoelectric conversion unit to the second photoelectric conversion unit. The reflective unit is disposed on a side surface of the multilayer interference filter.
    Type: Application
    Filed: July 7, 2014
    Publication date: August 27, 2015
    Inventors: Tatsuya OHGURO, Koichi KOKUBUN
  • Publication number: 20150118779
    Abstract: According to one embodiment, a strain and pressure sensing device includes a semiconductor circuit unit and a sensing unit. The semiconductor circuit unit includes a semiconductor substrate and a transistor. The transistor is provided on a semiconductor substrate. The sensing unit is provided on the semiconductor circuit unit, and has space and non-space portions. The non-space portion is juxtaposed with the space portion. The sensing unit further includes a movable beam, a strain sensing element unit, and first and second buried interconnects. The movable beam has fixed and movable portions, and includes first and second interconnect layers. The fixed portion is fixed to the non-space portion. The movable portion is separated from the transistor and extends from the fixed portion into the space portion. The strain sensing element unit is fixed to the movable portion. The first and second buried interconnects are provided in the non-space portion.
    Type: Application
    Filed: December 24, 2014
    Publication date: April 30, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hideaki FUKUZAWA, Tatsuya Ohguro, Akihiro Kojima, Yoshiaki Sugizaki, Mariko Takayanagi, Yoshihiko Fuji, Akio Hori, Michiko Hara