Abstract: Provided are a valve member and a milking machine-EH that are easy to wash. The valve member enables an internal passage to temporarily retain milk when the milking machine is in a negative pressure state, and enables the milk retained in the internal passage to be discharged when the milking machine is in a normal pressure state. The valve member is provided with a cap that is attached to the milking machine. The cap is provided with a partition wall that separates a first space on the milk inflow side and a second space on the milk outflow side. A through hole in the partition wall allows communication between the first space and the second space. A valve body disposed in the second space closes the through hole when the negative pressure state is established, and opens the through hole when the normal pressure state is established.

Abstract: To provide a manual breast pump capable of stabilizing movement of a handle while reducing burden on muscle resulting from a repetitive operation of the handle. A manual breast pump 2 has a main body 3 having a passage 312 through which extracted breast milk passes, a hood 4 connected to the main body 3 and placed onto a breast, a diaphragm 34 generating a negative pressure in the passage 312, a holding member 200 attached to the main body 3 and provided to be rotatable with respect to the main body 3, and a handle 5 for being operated thereby deforming the diaphragm 34, the handle being held by the holding member 200. When the holding member 200 rotates with respect to the main body 3, the handle 5 rotates with respect to the main body 3 together with the holding member 200.

Abstract: According to one embodiment, a parallel processor performs the row processes in parallel in a LDPC decode while performing the column processes in parallel in the LDPC decode, and a control circuit alternately repeats the parallel processes of the row process and the parallel processes of the column process as many times as the number of rows and columns in a check matrix and divides the parallel rows for the row process when the LDPC decode is started.

Abstract: According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.

Abstract: According to one embodiment, an error correction decoder includes a selecting section, calculating section, check section, and updating section. The selecting section selects data used for matrix processing applied to a process target row from LLR data stored in the first memory section based on a check matrix, and stores the data in a second memory section. The calculating section executes the matrix processing based on the data stored in the second memory section, and writes updated data back to the second memory section. The check section checks a parity based on a calculating result of the calculating section. The updating section updates the LLR data of the first memory section based on the updated data of the second memory section.

Abstract: A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information ? calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information ? stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Abstract: A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information ? calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information ? stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Abstract: A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.

Abstract: The present invention relates to an extruded thermoplastic resin foam, particularly relates to a board extruded thermoplastic resin which has low heat conductivity, an excellent heat insulating property over a long period of time, high flame retardancy, and excellent mechanical strength. The extruded thermoplastic resin foam having an apparent density of 20 to 50 kg/m3, a closed cells ratio of 85% or more and a thickness of 10 to 150 mm, and containing a non-halogen organic physical blowing agent, wherein the thermoplastic resin composing the extruded foam contains a mixture of 100 parts by weight of a polystyrene resin (A) and 5 to 150 parts by weight of a polyester resin (B), and an endothermic calorific value of the polyester resin (B) less than 5 J/g (including 0) for fusion of the polyester resin on a DSC curve obtained by heat flux differential scanning calorimetry based on JIS K7122 (1987).

Abstract: A method for producing an extruded heat-insulating foam board having a thickness of 10 to 150 mm, an apparent density of 20 to 50 kg/m3 and a closed cell content of at least 80% by extrusion foaming of a foamable resin melt containing a base resin composed primarily of a polystyrene resin, a physical blowing agent and a flame retardant, wherein 3 to 50 mol % of a hydrofluoroolefin, 30 to 70 mol % of a saturated hydrocarbon having 3 to 5 carbon atoms, and 5 to 50 mol % of water and/or carbon dioxide (where the sum of the contents of the hydrofluoroolefin, saturated hydrocarbon having 3 to 5 carbon atoms, water and/or carbon dioxide is 100 mol %) are used as the physical blowing agent. The extruded polystyrene resin heat-insulating foam board is produced with good extrusion foamability and moldability and has a high expansion ratio, a large thickness, excellent long-term heat-insulating properties and flame retardancy, and good appearance.

Abstract: An LDPC error detection/correction circuit according to an embodiment includes a selector that divides data into p groups based on a check matrix H including blocks made up of unit matrixes having a size p and shift blocks, a selector that divides a group into Y subgroups, a bit node storage section that stores LMEM variables to calculate a probability ? in association with each first address, a check node storage section that stores TMEM variables to calculate an external value ? in association with each second address, a rotator that performs rotation processing on the TMEM with a rotation value based on a shift value, and an operation circuit made up of (p/Y) operation units that perform parallel processing in subgroup units.

Abstract: A memory system having a memory card configured to store frame data composed of a plurality of pieces of sector data and a host configured to send and receive the frame data to and from the memory card, the memory card includes: an ECC1 decoder configured to perform BCH decoding processing with a hard decision code on a sector data basis; an ECC2 decoder configured to perform LDPC decoding processing with an LDPC code on a frame data basis; a sector error flag section configured to store information about presence or absence of error data in the BCH decoding processing; and an ECC control section configured to perform, in the LDPC decoding processing, control of increasing a reliability of sector data containing no error data based on the information in the sector error flag section.

Abstract: A semiconductor memory device includes a semiconductor memory unit which stores LDPC encoded data, and a decoding unit which decodes the encoded data, wherein the decoding unit performs serial decoding using the posterior likelihood ratio as it is for a column element likelihood ratio when the absolute value of the posterior likelihood ratio is not smaller than a threshold and using the column element likelihood ratio as it is for the posterior likelihood ratio when the absolute value of the column element likelihood ratio is not smaller than the threshold, and if the decoding does not succeed even after a predetermined first cycle count of iterative processing is performed or if the number of syndrome errors becomes smaller than a predetermined first syndrome error count, the decoding unit shrinks the absolute values of at least some of posterior likelihood ratios and resets all prior likelihood ratios to “0.

Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.

Abstract: A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information ? calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information ? stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N?2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N?2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.

Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N?2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.