Patents by Inventor Tatsuyuki Shinagawa

Tatsuyuki Shinagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9653589
    Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 16, 2017
    Assignees: FURUKAWA ELECTRIC CO., LTD., FUJI ELECTRIC CO., LTD.
    Inventors: Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryosuke Tamura, Shinya Ootomo
  • Patent number: 9276066
    Abstract: A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 1, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Ryosuke Tamura, Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryohei Makino, Jiang Li
  • Publication number: 20150221725
    Abstract: A semiconductor multi-layer substrate includes a substrate, a buffer layer formed on the substrate and made of a nitride semiconductor, an electric-field control layer formed on the buffer layer and made of a nitride semiconductor, the electric-field control layer having conductivity in the substrate's lateral direction, an electric-field relaxation layer formed on the electric-field control layer and made of a nitride semiconductor, and an active layer formed on the electric-field relaxation layer and made of an nitride semiconductor. A resistance in the substrate's lateral direction of the electric-field control layer is equal to or smaller than 10 times a resistance of the electric-field relaxation layer, and a ratio of an electric field share between the electric-field relaxation layer and the buffer layer is controlled by a ratio between a thickness of the electric-field relaxation layer and a thickness of the buffer layer.
    Type: Application
    Filed: July 5, 2013
    Publication date: August 6, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Ryosuke Tamura, Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryohei Makino, Jiang Li
  • Publication number: 20140374771
    Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.
    Type: Application
    Filed: September 10, 2014
    Publication date: December 25, 2014
    Applicants: Furukawa Electric Co., Ltd., Fuji Electric Co., Ltd.
    Inventors: Kazuyuki UMENO, Tatsuyuki Shinagawa, Keishi Takaki, Ryosuke Tamura, Shinya Ootomo
  • Patent number: 8884393
    Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Takuya Kokawa, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
  • Publication number: 20140084298
    Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.
    Type: Application
    Filed: July 10, 2013
    Publication date: March 27, 2014
    Inventors: Takuya KOKAWA, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
  • Patent number: 8222658
    Abstract: A semiconductor light emitting element of the present invention comprises: a zinc oxide (ZnO) single crystal substrate 12 with a substrate surface of a plane orientation insusceptible to a piezo electric field; a Lattice-matched layer 13 formed on the substrate surface to be lattice-matched with the ZnO single crystal substrate 12; an active layer 15 of indium gallium nitride (InxGa1-xN, 0<x<1); two of cladding layers 14 and 16 to be lattice-matched with the active layer 15 and/or the Lattice-matched layer 13.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: July 17, 2012
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Tatsuyuki Shinagawa, Hirotatsu Ishii, Akihiko Kasukawa
  • Patent number: 8222639
    Abstract: An interfacial reaction suppressing layer 12 formed between an oxide layer including a ZnO single crystal substrate 11 and a nitride layer including an InGaN semiconductor layer 13 restrains the interfacial reaction between the oxide layer and the nitride layer and formation of a reaction layer (Al2ZnO4) at the interface, which makes it possible to grow and thermally treat the InGaN semiconductor layer 13 at a high temperature. Thus, a crystal quality of the InGaN semiconductor layer 13 is improved.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: July 17, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Tatsuyuki Shinagawa, Hirotatsu Ishii, Akihiko Kasukawa
  • Patent number: 8093626
    Abstract: Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: January 10, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yuki Niiyama, Shinya Ootomo, Tatsuyuki Shinagawa, Takehiko Nomura, Seikoh Yoshida, Hiroshi Kambayashi
  • Publication number: 20110261849
    Abstract: A semiconductor light emitting element comprising: a buffer layer that is grown by using a growth substrate including ZnO, the buffer layer being made by using an AlGaInN-based material including In and being configured so that the growth surface thereof has a nitrogen polar plane; and an active layer that is formed on the buffer layer, the active layer being made by using an AlGaInN-based material including In and being configured so that the growth surface thereof has a group-III polar plane.
    Type: Application
    Filed: March 2, 2011
    Publication date: October 27, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Tatsuyuki Shinagawa, Hirotatsu Ishii, Hirokazu Sasaki, Akihiko Kasukawa
  • Publication number: 20100283083
    Abstract: Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.
    Type: Application
    Filed: June 14, 2007
    Publication date: November 11, 2010
    Inventors: Yuki Niiyama, Shinya Ootomo, Tatsuyuki Shinagawa, Takehiko Nomura, Seikoh Yoshida, Hiroshi Kambayashi
  • Publication number: 20100051939
    Abstract: An interfacial reaction suppressing layer 12 formed between an oxide layer including a ZnO single crystal substrate 11 and a nitride layer including an InGaN semiconductor layer 13 restrains the interfacial reaction between the oxide layer and the nitride layer and formation of a reaction layer (Al2ZnO4) at the interface, which makes it possible to grow and thermally treat the InGaN semiconductor layer 13 at a high temperature. Thus, a crystal quality of the InGaN semiconductor layer 13 is improved.
    Type: Application
    Filed: August 4, 2009
    Publication date: March 4, 2010
    Inventors: Tatsuyuki Shinagawa, Hirotatsu Ishii, Akihiko Kasukawa
  • Publication number: 20090224240
    Abstract: A semiconductor light emitting element of the present invention comprises: a zinc oxide (ZnO) single crystal substrate 12 with a substrate surface of a plane orientation insusceptible to a piezo electric field; a Lattice-matched layer 13 formed on the substrate surface to be lattice-matched with the ZnO single crystal substrate 12; an active layer 15 of indium gallium nitride (InxGa1-xN, 0<x<1); two of cladding layers 14 and 16 to be lattice-matched with the active layer 15 and/or the Lattice-matched layer 13.
    Type: Application
    Filed: March 6, 2009
    Publication date: September 10, 2009
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Tatsuyuki Shinagawa, Hirotatsu Ishi, Akihiko Kasukawa
  • Patent number: 7215693
    Abstract: A surface emitting semiconductor laser device including a substrate, a bottom DBR, and a mesa post having a layer structure, the layer structure including a top DBR including a plurality of pairs, each of said pairs including an Al-containing high-reflectivity layer and an Al-containing low-reflectivity layer, an active layer structure sandwiched between the DBRs for emitting laser, and a current confinement layer disposed within or in a vicinity of one of the DBRs, the current confinement layer including a central current injection area and an annular current blocking area encircling the central current injection area, the annular current blocking area being formed by selective oxidation of Al in an AlXGa1-XAs layer (0.95?x<1) having a thickness below 60 nm, the Al-containing low-reflectivity layer including Al at an atomic ratio not more than 0.8 and below 0.9.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 8, 2007
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Norihiro Iwai, Tatsuyuki Shinagawa, Noriyuki Yokouchi
  • Publication number: 20050220160
    Abstract: A vertical cavity surface emitting semiconductor laser (VCSEL) device has p-type and n-type DBRs sandwiching therebetween a resonant cavity including an active layer. Each the DBRs has a plurality of layer pairs each including a Alx1Ga1-x1As high-reflectivity layer and an Alx2Ga1-x2As low-reflectivity layer and an Alx3Ga1-x3As slope content layer interposed between each of the high-reflectivity layers and adjacent low-reflectivity layer. The slope content layers in the vicinity of the active layer has an Al content x3 wherein 0<x3?0.3 and 0.55?x3<1 and an impurity concentration of 3×1017 cm?3 or above.
    Type: Application
    Filed: May 27, 2005
    Publication date: October 6, 2005
    Applicant: The Furukawa Electric Co., Ltd.
    Inventors: Tatsuyuki Shinagawa, Norihiro Iwai, Noriyuki Yokouchi
  • Patent number: 6914925
    Abstract: A vertical cavity surface emitting semiconductor laser (VCSEL) device has p-type and n-type DBRs sandwiching therebetween a resonant cavity including an active layer. Each the DBRs has a plurality of layer pairs each including a Alx1Ga1-x1As high-reflectivity layer and an Alx2Ga1-x2As low-reflectivity layer and an Alx3Ga1-x3As slope content layer interposed between each of the high-reflectivity layers and adjacent low-reflectivity layer. The slope content layers in the vicinity of the active layer has an Al content x3 wherein 0<x3?0.3 and 0.55?x3<1 and an impurity concentration of 3×1017 cm?3 or above.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: July 5, 2005
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Tatsuyuki Shinagawa, Norihiro Iwai, Noriyuki Yokouchi
  • Publication number: 20050041713
    Abstract: A surface emitting semiconductor laser device including a substrate, a bottom DBR, and a mesa post having a layer structure, the layer structure including a top DBR including a plurality of pairs, each of said pairs including an Al-containing high-reflectivity layer and an Al-containing low-reflectivity layer, an active layer structure sandwiched between the DBRs for emitting laser, and a current confinement layer disposed within or in a vicinity of one of the DBRs, the current confinement layer including a central current injection area and an annular current blocking area encircling the central current injection area, the annular current blocking area being formed by selective oxidation of Al in an AlXGa1-XAs layer (0.95?x<1) having a thickness below 60 nm, the Al-containing low-reflectivity layer including Al at an atomic ratio not more than 0.8 and below 0.9.
    Type: Application
    Filed: July 27, 2004
    Publication date: February 24, 2005
    Inventors: Norihiro Iwai, Tatsuyuki Shinagawa, Noriyuki Yokouchi
  • Patent number: 6839369
    Abstract: A surface emitting semiconductor laser device including a substrate, a bottom DBR, and a mesa post having a layer structure, the layer structure including a top DBR including a plurality of pairs, each of said pairs including an Al-containing high-reflectivity layer and an Al-containing low-reflectivity layer, an active layer structure sandwiched between the DBRs for emitting laser, and a current confinement layer disposed within or in a vicinity of one of the DBRs, the current confinement layer including a central current injection area and an annular current blocking area encircling the central current injection area, the annular current blocking area being formed by selective oxidation of Al in an AlxGa1?xAs layer (0.95?x<1) having a thickness below 60 nm, the Al-containing low-reflectivity layer including Al at an atomic ratio not more than 0.8 and below 0.9.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: January 4, 2005
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Norihiro Iwai, Tatsuyuki Shinagawa, Noriyuki Yokouchi
  • Patent number: 6829274
    Abstract: A surface emitting semiconductor laser device of oxidized-Al current confinement structure has a resonant wavelength of a fundamental transverse mode, which is set shorter than or equal to a peak-gain wavelength of the laser device at a specified temperature. The surface emitting semiconductor laser device emits in a single-transverse mode.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: December 7, 2004
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Natsumi Ueda, Noriyuki Yokouchi, Tatsuyuki Shinagawa
  • Patent number: 6700914
    Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a pair of diffusion Bragg reflectors (DBRs) sandwiching therebetween a multiple quantum well (MQW) comprising active layers. The bottom DBR includes a lower layer structure having AlAs layers having a higher thermal conductivity and AlGaAs layers in pair and an upper layer structure acting anti-oxidation layers and having a pair of AlGaAs layers having different Al contents. A selectively oxidized AlAs layer disposed as the top layer of the bottom DBR comprises an Al-oxidized area and a non-oxidized layer for confinement of current injection path.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: March 2, 2004
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Noriyuki Yokouchi, Masato Tachibana, Natsumi Ueda, Tatsuyuki Shinagawa