Abstract: Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame.

Abstract: Methods of forming pre-encapsulated frames comprise flowing a dielectric encapsulation material around at least one conductive trace. A cavity configured to receive at least one semiconductor device at least partially in the cavity is formed in the encapsulation material. A first connection area of the at least one trace is exposed within the cavity. At least another connection area of the at least one trace is exposed laterally adjacent to the cavity. The dielectric encapsulation material is hardened to form a pre-encapsulated frame.

Abstract: A pre-encapsulated cavity interposer, a pre-encapsulated frame, for a semiconductor device.

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Abstract: A pre-encapsulated cavity interposer, a pre-encapsulated frame, for a semiconductor device.

Abstract: A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of semiconductor device components (e.g., semiconductor devices) may be assembled with the interposer. For example, at least one contact pad of a semiconductor device component adjacent to one surface of the interposer may be electrically connected to a corresponding contact pad of another semiconductor device component positioned adjacent to an opposite surface of the interposer. As another example, multiple semiconductor device components may be at least partially superimposed relative to one another and at least partially disposed within a receptacle of the interposer.

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing thereof are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes stacking a first die package having a first dielectric casing on top of a second die package having a second dielectric casing, aligning first metal leads at a lateral surface of the first casing with second metal leads at a second lateral surface of the second casing, and forming metal solder connectors that couple individual first leads to individual second leads. In another embodiment, the method of manufacturing the microelectronic device may further include forming the connectors by applying metal solder to a portion of the first lateral surface, to a portion of the second lateral surface, and across a gap between the first die package and the second die package so that the connectors are formed by the metal solder wetting to the individual first leads and the individual second leads.

Abstract: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.

Abstract: An interposer includes a substantially planar substrate with a slot therethrough. The slot includes a laterally recessed area in only a portion of a periphery thereof at a location that exposes at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area may facilitate access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, and then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.

Abstract: Various aspects of the invention provide temporary interfaces for microelectronic components, microelectronic component test systems, and methods of testing microelectronic components. One of the disclosed temporary interfaces employs a substrate having a plurality of terminals and a switch layer carrying a plurality of actuatable liquid switches. These switches may be adapted to conform to a surface of a component terminal to electrically connect the component terminal to a terminal of the substrate. Another adaptation provides a microelectronic component test system including a microelectronic component including a plurality of terminals. A body is juxtaposed with, but spaced from, the microelectronic component. The body carries a plurality of conduits and a conformable conductor is associated with each conduit. Each of these conformable conductors comprises a volume of electrically conductive liquid and the associated conduit.

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed.

Abstract: An interposer including a substantially planar substrate element with a slot formed therethrough. The slot, through which bond pads of a semiconductor die are exposed upon assembly of the interposer with the semiconductor die, includes a laterally recessed area formed in only a portion of a periphery thereof. The laterally recessed area is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad located adjacent an outer periphery of the semiconductor die and the outer periphery. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. Semiconductor device assemblies and packages that include the interposer are also disclosed, as are methods for assembling semiconductor device components with the interposer and methods for packaging such assemblies.

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.

Abstract: Methods for packaging microelectronic devices and microelectronic devices formed by such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of microelectronic dies to a support member, covering the dies and at least a portion of the support member with a dielectric layer, forming a plurality of vias through the dielectric layer between the dies, and fabricating a plurality of conductive links in corresponding vias. In another embodiment, a plurality of microelectronic devices includes a support member, a plurality of microelectronic dies coupled to the support member, a dielectric layer over the dies and at least a portion of the support member, and a plurality of conductive links extending from a first surface of the dielectric layer to a second surface. The dies include an integrated circuit and a plurality of bond-pads coupled to the integrated circuit, and the conductive links are disposed between the dies.

Abstract: An interposer includes a substantially planar substrate with a slot formed therethrough. The slot includes a laterally recessed area formed in only a portion of a periphery thereof, which is positioned so as to expose at least a portion of an active surface of the semiconductor die located between a bond pad and an outer periphery of the semiconductor die. The laterally recessed area facilitates access to the bond pad by apparatus for forming, positioning, or securing intermediate conductive elements. The slot may be formed by forming a first, thin elongated slot through the interposer substrate, then widening a portion thereof. Alternatively, a first, small circular hole may be formed through the interposer substrate, then an elongated slot having a width that exceeds the diameter of the small circular hole may be formed through the substrate at a location which is continuous with the small circular hole.