Abstract: A driving circuit and a common electrode are located within a sealant region of the first substrate, wherein the driving circuit includes switch devices and turn-line structures. The common electrode is located within the sealant region of the first substrate. The planar layer is located on the first substrate, wherein the thickness of the planar layer at the turn-line structure of the driving circuit is less than the thicknesses of other portions. The conductive layer is located on the planar layer. A second substrate having an electrode thereon is disposed opposite to the first substrate. A liquid crystal layer is located within the display region between the first substrate and the second substrate. A sealant is located within the sealant region between the first substrate and the second substrate, and conductive balls are distributed in the sealant.

Abstract: A pixel structure disposed on a substrate includes a gate, a patterned dielectric layer, a patterned semiconductor layer, a patterned metal layer, an overcoat layer and a transparent pixel electrode. The patterned dielectric layer and the gate covered thereby are disposed on the substrate. The patterned semiconductor layer on the patterned dielectric layer includes bumps and a channel above the gate. The patterned metal layer includes a source, a drain and a reflective pixel electrode connecting the drain. The source and the drain cover a portion of the channel. The reflective pixel electrode covers the bumps. The gate, the patterned dielectric layer, the patterned semiconductor layer and the patterned metal layer form a transistor on which the overcoat layer has a contact hole exposing a portion of the reflective pixel electrode. The transparent pixel electrode on the overcoat layer electrically connects the reflective pixel electrode through the contact hole.

Abstract: A pixel structure of a display panel is provided. The pixel structure includes a first storage capacitor formed by a pixel electrode and a common electrode pattern, and a second storage capacitor formed by an electrode pattern and the common electrode pattern. Accordingly, the storage capacitance is greatly improved without sacrificing the aperture ratio, or the aperture ratio is improved by reducing the area of the storage capacitor while the storage capacitance is maintained.

Abstract: A pixel structure disposed on a substrate includes a gate, a patterned dielectric layer, a patterned semiconductor layer, a patterned metal layer, an overcoat layer and a transparent pixel electrode. The patterned dielectric layer and the gate covered thereby are disposed on the substrate. The patterned semiconductor layer on the patterned dielectric layer includes bumps and a channel above the gate. The patterned metal layer includes a source, a drain and a reflective pixel electrode connecting the drain. The source and the drain cover a portion of the channel. The reflective pixel electrode covers the bumps. The gate, the patterned dielectric layer, the patterned semiconductor layer and the patterned metal layer form a transistor on which the overcoat layer has a contact hole exposing a portion of the reflective pixel electrode. The transparent pixel electrode on the overcoat layer electrically connects the reflective pixel electrode through the contact hole.