Patents by Inventor Te-Hsin Chiu

Te-Hsin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220293599
    Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first fin protruding from the semiconductor substrate and extending along a first direction. The semiconductor device includes a second fin protruding from the semiconductor substrate and extending along the first direction. A first epitaxial source/drain region coupled to the first fin and a second epitaxial source/drain region coupled to the second fin are laterally spaced apart from each other by an air void.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Te-Hsin Chiu, Kam-Tou Sio, Jiann-Tyng Tzeng
  • Publication number: 20220284164
    Abstract: In some embodiments, portions of a pattern, generated in a layout process, of a layer in an integrated circuit, such as those of a layer of metallic power lines in a power grid (PG), are removed after the layout process through a computer-implemented process analogous to solving the N-coloring problem. Through this post-processing removal process, pattern portions can be removed so as reduce the coverage of the layer in the fabricated integrated circuit to a desired extent without producing certain harmful effects, such as severing a powerline.
    Type: Application
    Filed: November 30, 2021
    Publication date: September 8, 2022
    Inventors: Shih-Wei Peng, Te-Hsin Chiu, Jiann-Tyng Tzeng
  • Publication number: 20220262719
    Abstract: An integrated circuit includes a plurality of first layer deep lines and a plurality of first layer shallow lines. The integrated circuit also includes a plurality of second layer deep lines and a plurality of second layer shallow lines. Each of the first layer deep lines and the first layer shallow lines is in a first conductive layer. Each of the second layer deep lines and the second layer shallow lines is in a second conductive layer above the first conductive layer.
    Type: Application
    Filed: June 10, 2021
    Publication date: August 18, 2022
    Inventors: Wei-An LAI, Te-Hsin CHIU, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG, Chia-Tien WU
  • Publication number: 20220254770
    Abstract: An integrated circuit includes a first-type active-region structure, a second-type active-region structure on a substrate, and a plurality of gate-conductors. The integrated circuit also includes a backside horizontal conducting line in a backside first conducting layer below the substrate, a backside vertical conducting line in a backside second conducting layer below the backside first conducting layer, and a pin-connector for a circuit cell. The pin-connector is directly connected between the backside horizontal conducting line and the backside vertical conducting line. The backside horizontal conducting line extends across a vertical boundary of the circuit cell.
    Type: Application
    Filed: June 10, 2021
    Publication date: August 11, 2022
    Inventors: Wei-An LAI, Shih-Wei PENG, Te-Hsin CHIU, Jiann-Tyng TZENG, Chung-Hsing WANG
  • Publication number: 20220237359
    Abstract: An integrated circuit includes a first power rail, a first signal line, a first transistor and a second transistor. The first power rail is on a back-side of a substrate and is configured to supply a first supply voltage. The first signal line is on the back-side of the substrate and is separated from the first power rail. The first transistor has a first active region in a front-side of the substrate. The first active region is overlapped by the first power rail and is electrically coupled to the first power rail. The second transistor has a second active region that is in the front-side of the substrate. The second active region is separated from the first active region, is overlapped by the first signal line, and is configured to receive the first supply voltage of the first power rail through the first active region of the first transistor.
    Type: Application
    Filed: June 11, 2021
    Publication date: July 28, 2022
    Inventors: Shih-Wei PENG, Te-Hsin CHIU, Jiann-Tyng TZENG
  • Publication number: 20220238371
    Abstract: A method includes: doping a region through a first surface of a semiconductor substrate; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors comprises one or more source/drain structures electrically coupled to the doped region through a corresponding one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting signals present on the doped region through a second surface of the semiconductor substrate, the second surface opposite to the first surface.
    Type: Application
    Filed: November 22, 2021
    Publication date: July 28, 2022
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-An Lai, Jiann-Tyng Tzeng
  • Publication number: 20220238679
    Abstract: A semiconductor device and a method of manufacturing the device are disclosed. In one aspect, the semiconductor device includes a first active region that extends along a first lateral direction and includes a plurality of first epitaxial structures. The semiconductor device also includes an interconnect structure that also extends along the first lateral direction and is disposed below the first active region, wherein at least one of the plurality of first epitaxial structures is electrically coupled to the interconnect structure. The interconnect structure includes at least a first portion that offsets from the first active region along a second lateral direction perpendicular to the first lateral direction.
    Type: Application
    Filed: November 16, 2021
    Publication date: July 28, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Wei-An Lai, Jiann-Tyng Tzeng
  • Patent number: 11374005
    Abstract: A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. The first transistor is arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device also includes a first conductive line arranged in a third layer between the first layer and the second layer and extending in the second direction, wherein the first conductive line is configured to electrically connect a first source/drain region of the first active region to a second source/drain region of the second active region.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: June 28, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Te-Hsin Chiu, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Publication number: 20220130822
    Abstract: Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
    Type: Application
    Filed: June 11, 2021
    Publication date: April 28, 2022
    Inventors: Te-Hsin CHIU, Kam-Tou SIO, Shang-Wei FANG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Publication number: 20220122971
    Abstract: A semiconductor device includes a first transistor of a first conductivity type and a second transistor of a second conductivity type. The first transistor is arranged in a first layer and includes a gate extending in a first direction and a first active region extending in a second direction perpendicular to the first direction. The second transistor is arranged in a second layer over the first layer and includes the gate and a second active region extending in the second direction. The semiconductor device also includes a first conductive line arranged in a third layer between the first layer and the second layer and extending in the second direction, wherein the first conductive line is configured to electrically connect a first source/drain region of the first active region to a second source/drain region of the second active region.
    Type: Application
    Filed: October 20, 2020
    Publication date: April 21, 2022
    Inventors: SHIH-WEI PENG, TE-HSIN CHIU, WEI-CHENG LIN, JIANN-TYNG TZENG
  • Publication number: 20220122993
    Abstract: A memory device is provided. The memory device includes first and second pull-up transistors. The first pull-up transistor is disposed over a semiconductor substrate, and including a first gate structure and two first source/drain structures at opposite sides of the first gate structure. The second pull-up transistor is laterally spaced apart from the first pull-up transistor, and including a second gate structure and two second source/drain structures at opposite sides of the second gate structure. The first and second gate structures extend along a first direction and laterally spaced apart from each other along a second direction intersected with the first direction. The first gate structure further extends along a sidewall of one of the second source/drain structures, and the second gate structure further extends along a sidewall of one of the first source/drain structures.
    Type: Application
    Filed: October 21, 2020
    Publication date: April 21, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Hsin Chiu, Jiann-Tyng Tzeng, Shih-Wei Peng, Wei-An Lai
  • Publication number: 20220115391
    Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang
  • Publication number: 20220115324
    Abstract: An integrated circuit includes a first, second and third active region and a first, second and third conductive line. The first, second and third active regions extend in a first direction, and are on a first level of a front-side of a substrate. The second active region is between the first active region and the third active region. The first and second conductive line extend in the first direction, and are on a second level of a back-side of the substrate. The first conductive line is between the first and second active region. The second conductive line is between the second and third active region. The third conductive line extends in the second direction, is on a third level of the back-side of the substrate, overlaps the first and second conductive line, and electrically couples the first and second active regions.
    Type: Application
    Filed: April 22, 2021
    Publication date: April 14, 2022
    Inventors: Te-Hsin CHIU, Kam-Tou SIO, Shih-Wei PENG, Wei-Cheng LIN, Jiann-Tyng TZENG
  • Patent number: 11302631
    Abstract: An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Te-Hsin Chiu, Shih-Wei Peng, Jiann-Tyng Tzeng
  • Publication number: 20220068791
    Abstract: The present disclosure provides a semiconductor structure, including a substrate, a first metal line over the substrate and extending along a first direction, a protection layer lining a sidewall of the first metal line, a second metal line above the first metal line and extending along the first direction, and a third metal line above the second metal line, extending along a second direction perpendicular to the first direction.
    Type: Application
    Filed: December 16, 2020
    Publication date: March 3, 2022
    Inventors: Te-Hsin CHIU, Wei-An LAI, Meng-Hung SHEN, Wei-Cheng LIN, Jiann-Tyng TZENG, Kam-Tou SIO
  • Publication number: 20220037252
    Abstract: An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Inventors: TE-HSIN CHIU, SHIH-WEI PENG, JIANN-TYNG TZENG
  • Patent number: 11211388
    Abstract: A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Han Lin, Te-Hsin Chiu, Wei-Cheng Wu, Li-Feng Teng, Chien-Hung Chang
  • Publication number: 20210343697
    Abstract: A method generating the layout diagram includes: selecting gate patterns for which a first distance from a corresponding VG pattern to a corresponding cut-gate section is equal to or greater than a first reference value; and for each of the selected gate patterns, increasing a size of the corresponding cut-gate section from a first value to a second value; the second value resulting in a first type of overhang of a corresponding remnant portion of the corresponding gate pattern; and the first type of overhang being a minimal permissible amount of overhang of the corresponding remnant portion beyond the corresponding first or second nearest active area pattern. A result is that gaps between ends of corresponding ends of remnants of gate patters are expanded.
    Type: Application
    Filed: December 1, 2020
    Publication date: November 4, 2021
    Inventors: Te-Hsin CHIU, Shih-Wei PENG, Jiann-Tyng TZENG
  • Publication number: 20210343650
    Abstract: An IC package includes a first die including a front side and a back side, the front side including a first signal routing structure, the back side including a first power distribution structure, and a second die including a front side and a back side, the front side including a second signal routing structure, the back side including a second power distribution structure. The IC package includes a third power distribution structure positioned between the first and second power distribution structures and electrically connected to each of the first and second power distribution structures.
    Type: Application
    Filed: February 17, 2021
    Publication date: November 4, 2021
    Inventors: Shih-Wei PENG, Te-Hsin CHIU, Jiann-Tyng TZENG
  • Publication number: 20210343744
    Abstract: An integrated circuit includes a set of power rails on a back-side of a substrate, a first flip-flop, a second flip-flop and a third flip-flop. The set of power rails extend in a first direction. The first flip-flop includes a first set of conductive structures extending in the first direction. The second flip-flop abuts the first flip-flop at a first boundary, and includes a second set of conductive structures extending in the first direction. The third flip-flop abuts the second flip-flop at a second boundary, and includes a third set of conductive structures extending in the first direction. The first, second and third flip-flop are on a first metal layer and are on a front-side of the substrate opposite from the back-side. The second set of conductive structures are offset from the first boundary and the second boundary in a second direction.
    Type: Application
    Filed: February 25, 2021
    Publication date: November 4, 2021
    Inventors: Te-Hsin CHIU, Wei-Cheng LIN, Wei-An LAI, Jiann-Tyng TZENG