Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bit line and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bit line can include a first bit line segment coupled to the first memory string group and a second bit line segment coupled to the second memory string group. The buffer can be coupled to the memory array by the bit line. The memory array and the buffer can be included in separate first and second dies, respectively, and the first die can be bonded to the second die.

Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.

Abstract: Disclosed is a biped robot and multi-configuration robot capable of being spliced autonomously, and a control method of the multi-configuration robot. The biped robot comprises a torso, arms, legs, a tolerance docking sleeve, and a torso docking device. The arms are correspondingly arranged at the left and right sides of the torso, and two legs are arranged at the lower side of the torso. The tolerance docking sleeve is movably arranged at the rear side of the torso through a base, and the torso docking device is fixed to the front side of the torso. Single biped robots in the present disclosure can form a multi-configuration legged combined body in a self-organization and reconstruction mode so as to achieve bipedal, quadrupedal, hexapodal and other multi-legged configurations. The motion stability and the load capacity of the legged robot are improved through the splicing combination of the modular legged robots.

Abstract: A semiconductor device includes a substrate, a plurality of bit lines, a plurality of contacts, a plurality of storage node pads, a capacitor structure and a plurality of first interface layers. The bit lines and the contacts are disposed on the substrate, and the contacts are alternately and separately disposed with the bit lines. The storage node pads are disposed on the contacts and the bit lines, and are respectively aligned with the contacts. The capacitor structure is disposed on the storage node pads. The first interface layers are disposed between the storage node pads and the capacitor structure, and the first interface layers include a metal nitride material. The first interface layers may improve the granular size of the storage node pads, and reduce the surface roughness thereof, and further improve the electrical connection between the storage nodes and transistor components below.

Abstract: A semiconductor memory device includes a substrate and a capacitor. The capacitor is disposed on the substrate, and the capacitor includes a bottom electrode layer, a capacitor dielectric layer and a top electrode layer sequentially stacked from bottom to top and an aluminum-containing insulation layer. The aluminum-containing insulation layer includes aluminum titanium nitride or aluminum oxynitride, and is in direct contact with the capacitor dielectric layer and disposed between the bottom electrode layer and the top electrode layer. Therefore, the semiconductor memory device may effectively improve the leakage current.

Abstract: A display substrate and a manufacturing method therefor, and a display device. The display substrate comprises a stretchable area, the stretchable area comprises multiple pixel island areas spaced apart from each other, multiple hole areas, and connection bridge areas located between the pixel island areas and the hole areas; each of the hole areas is provided with one or more openings, and comprises a composite structural layer stacked on the substrate, each of the openings penetrates through the composite structural layer and a part of the opening is provided in the substrate, the opening penetrates through or does not penetrate through the substrate, and the wall of the opening is provided with separation grooves; and each of the hole areas further comprises a functional film layer provided on the composite structural layer and on the wall of each opening, and the functional film layer is separated at the separation grooves.

Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path.

Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.

Abstract: The present disclosure provides page buffer circuits of 3D NAND devices. In some embodiments, the page buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment of a bit line, and a second bit line segment sensing branch connected to a second bit line segment of the bit line. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit. In some embodiments, the first bit line segment sensing branch comprises a first sense latch and a first bit line pre-charge path, and the second bit line segment sensing branch comprises a second sense latch and a second bit line pre-charge path.

Abstract: The present disclosure provides buffer circuits of 3D NAND memory device. In some embodiments, the buffer circuit comprises a first bit line segment sensing branch connected to a first bit line segment and including a low-voltage latch, and a second bit line segment sensing branch connected to a second bit line segment and including a sensing latch. The first bit line segment sensing branch and the second bit line segment sensing branch are parallel connected to a sensing node of the page buffer circuit.

Abstract: The disclosure discloses a touch panel, a display panel and a display device. A plurality of touch electrodes, a bonding region and a plurality of touch wires are included, where one touch wire is electrically connected to one touch electrode; and a touch group is formed by an ith touch electrode and an n-i+1th touch electrode in a touch electrode column, touch wires electrically connected to two touch electrodes in a same touch group are arranged adjacently.

Abstract: A shift register unit, configured to generate a first gate drive signal and a second gate drive signal, which includes a first control circuit, configured to control a potential of a first node; a second control circuit, configured to control a potential of a second node; a first output circuit, configured to generate the first gate drive signal based on a first voltage signal provided by a first voltage terminal under the control of the potentials of the first and second nodes, and output the first gate drive signal through a first gate drive signal output terminal, wherein the first voltage signal provided by the first voltage terminal is a high level signal; and a second output circuit, configured to generate a second gate drive signal based on a second voltage signal provided by a second voltage terminal under the control of a potential of a control node, and output the second gate drive signal through a second gate drive signal output terminal.

Abstract: The present invention provides a semiconductor memory device and a fabricating method thereof. The semiconductor memory device includes a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.

Abstract: A multifunctional shaft apparatus includes a shaft base, a spindle, a tool holder, an ultrasonic vibration assembly, a laser light source and a mirror assembly. The spindle is disposed in the shaft base. The spindle has a laser channel extending along the spindle. The tool holder is disposed on the spindle. The tool holder has a hollow passage, an inner space and a recessed portion. The hollow passage is communicated with the laser channel. An inner wall of the hollow passage has at least one through hole communicated with the inner space, and the recessed portion is disposed on a bottom surface of the tool holder. The bottom surface has a light outlet. The ultrasonic vibration assembly includes a vibration member disposed in the recessed portion. The mirror assembly is disposed in the tool holder and is configured to reflect the laser light beam generated by the laser light source.

Abstract: Aspects of the disclosure provide a memory device. For example, the memory device can include a memory array, a bitline and a buffer. The memory array can include a plurality of memory strings. The memory strings can be divided into a first memory string group and a second memory string group. The bitline can include a first bitline segment coupled to the first memory string group and a second bitline segment coupled to the second memory string group. The first bitline segment can be disposed between the first memory string group and the buffer and be connected to the buffer through a first conduction path. The second bitline segment can be disposed between the second memory string group and the buffer and be connected to the buffer through a second conduction path.

Abstract: The present invention relates to an assembled, downward-pressing, multifunctional electroencephalogram (EEG) cap, at least comprising: a cap body, configured to be worn on a head of a patient, and formed by a plurality of constituent blocks, wherein each of the constituent blocks comprises a first unit and a second unit that carry extracranial electrodes for detecting EEG signals from corresponding areas of the head of the patient, in which the first unit and the second unit are configured to perform relative movements and thereby change their relative positions, the first unit and the second unit being shaped to fit a curved surface of the head of the patient; the first unit of the constituent block being movably connected to the second unit by means of a drive system provided between at least a part of the first unit and a part of the second unit, wherein the extracranial electrodes located on the first unit and on the second unit are configured to at least follow the relative movements between the first un

Abstract: The present disclosure provides a display panel and preparing method thereof, and a display apparatus. In one or more embodiments, the display panel includes a substrate that includes an off-screen camera region including a plurality of opening regions, a flexible layer located at a side of the substrate, a backplate layer located at a side of the flexible layer away from the substrate and including a plurality of light-transmitting film layers, and a light-emitting device layer located at a side of the backplate layer away from the substrate and including a plurality of cathodes. An orthographic projection of the flexibly layer on the substrate is not overlapped with the opening regions. An orthographic project of at least one light-transmitting film layer on the substrate covers the opening regions. Orthographic projections of the cathodes on the substrate are not overlapped with the opening regions.

Abstract: A pixel circuit includes a driving circuit, configured to drive a light-emitting element to emit light; a compensation control circuit, electrically connected to a first gate line and configured to control a control terminal of the driving circuit to be connected with a second terminal of the driving circuit under the control of a first gate drive signal provided by the first gate line; and a data writing circuit, electrically connected to a second gate line and configured to control a data voltage to be provided to a first terminal of the driving circuit under the control of a second gate drive signal provided by the second gate line. A voltage value of the first gate drive signal is substantially different from a voltage value of the second gate drive signal.

Abstract: The present disclosure provides a rehabilitation training equipment and a rehabilitation training system. The rehabilitation training equipment includes a driving device, a back placement device, a leg aid device, a cushion device, a first feedback device, and a control device. The driving device is configured to adjust rotation angles between the back placement device, the cushion device, and the leg aid device to achieve a posture training mode selected from a plurality of posture training modes including a standing mode, a sitting-up mode, and a lying mode. The first feedback device is used to obtain core muscle strength parameters of the human body. The control device is electrically connected to the first feedback device and the driving device, and is configured to obtain the core muscle strength parameters and send a control signal to the driving device.

Abstract: A display panel includes an array substrate, an OLED light-emitting layer and a color filter structure laminated in sequence, the color filter structure including a color filter layer, a black matrix and a heat conducting layer, wherein the color filter layer and the black matrix are disposed in a same layer, the heat conducting layer is disposed on at least one side of the black matrix and configured to conduct heat from the black matrix to a periphery of the color filter structure.