Abstract: A power supply saving system includes a power input interface, a power output interface, an alternating current/direct current (AC/DC) converter, a relay, a relay driving circuit, a trigger, and a timing sequence circuit. The AC/DC converter is capable of transforming the AC power signal to direct current (DC) power to supply to the relay, the relay driving circuit, the trigger, and the timing sequence circuit. The timing sequence circuit is capable of controlling the relay driving circuit via the trigger to turn on the relay to connect the power input interface to the power output interface when the timing sequence circuit receives a power-on signal. The timing sequence circuit is capable of controlling the relay driving circuit via the trigger to turn off the relay to cut off connection between the power input interface and the power output interface when the timing sequence circuit receives a power-off signal.

Abstract: The conversion device is connected, by a wired or wireless means, to an input/output port of a computing device installed with an instant messaging software. As instant messages are exchanged, the conversion device is activated by the instant messaging software to produce audio and/or visual responses in accordance with specific texts, symbols, and graphical images contained in the messages received. The conversion device could have an appealing appearance such as a doll, a puppet, or a toy figure. The conversion device can further contain at least an actuation mechanism such that, when activated, the conversion device sends a specific signal to the instant messaging software which encodes and packages the signal into a message and delivers the message to a remote computing device.

Abstract: A computing device whose components are separately housed in a main enclosure and at least a secondary enclosure is provided herein. The motherboard, power supply, adaptor card, hard disk drive, etc., are housed in the main enclosure while the peripheral storage devices of the computing device such as optical disk drives and hard disk drives are placed in at least a secondary enclosure. An appropriate signal link is maintained between the main enclosure and the secondary enclosure so that the components in the main enclosure could access the peripheral storage device in the secondary enclosure. Additionally, the secondary enclosure could be connected to another device such as a second computer or a TV so as to share the peripheral storage device in the secondary enclosure.

Abstract: An enclosure for housing various components of a computing device is provided herein, which contains at least three L-shaped corner members, at least three elongated wall members, a top cover member, and a bottom cover member. The corner members and the wall members are interleaved and joined to form a polygonal circumference for the enclosure. The top and bottom cover members are fixed to the top and bottom of the circumference respectively into a closed, polygonal-shaped enclosure so that a component of the computing device such as the motherboard, optical disk drive, hard disk drive, etc., could be housed therewithin.

Abstract: A computing device whose components are separately housed in a main enclosure and at least a secondary enclosure is provided herein. The motherboard, power supply, adaptor card, hard disk drive, etc., are housed in the main enclosure while the peripheral storage devices of the computing device such as optical disk drives and hard disk drives are placed in at least a secondary enclosure. An appropriate signal link is maintained between the main enclosure and the secondary enclosure so that the components in the main enclosure could access the peripheral storage device in the secondary enclosure. Additionally, the secondary enclosure could be connected to another device such as a second computer or a TV so as to share the peripheral storage device in the secondary enclosure.

Abstract: An enclosure for housing various components of a computing device is provided herein, which contains at least three L-shaped corner members, at least three elongated wall members, a top cover member, and a bottom cover member. The corner members and the wall members are interleaved and joined to form a polygonal circumference for the enclosure. The top and bottom cover members are fixed to the top and bottom of the circumference respectively into a closed, polygonal-shaped enclosure so that a component of the computing device such as the motherboard, optical disk drive, hard disk drive, etc., could be housed therewithin.

Abstract: A method for manufacturing a MOS device with improved well control stability. The method includes the steps of providing a semiconductor substrate; forming a gate electrode according to a critical dimension on the semiconductor substrate, wherein the gate electrode comprises a gate oxide layer and a conducting gate; inspecting a real dimension of the conducting gate; determining a thickness of subsequently formed conducting gate spacers according to the real dimension of the conducting gate, such that variations of electric characteristics of the device affected by the critical dimension of the conducting gate are reduced; and forming the conducting gate spacers with the determined thickness on sidewalls of the gate electrode.

Abstract: A novel process for isolating devices on a semiconductor substrate is disclosed. An isolation layer is first formed over the semiconductor substrate and patterned into at least two isolation mesas on the substrate. Next, a blanket semiconductor layer is formed over the substrate with a thickness sufficient to cover the isolation mesas. The semiconductor layer is subjected to planarization until the isolation mesas are exposed, thus resulting in a semiconductor region between the two isolation mesas to serve as an active region for semiconductor devices.

Abstract: A page buffer facilitates programming of a memory cell within an associated memory array by selectively connecting a bit line associated with the memory cell to a negative voltage supply in response to the logic state of a data signal. The page buffer includes an SRAM latch having first and second nodes, a cross-coupled latch having first and second nodes, and a pass transistor. The first node of the SRAM latch is coupled to receive the data signal and to a first control terminal of the cross-coupled latch. The second node of the SRAM latch is coupled to a second control terminal of the cross-coupled latch. The second node of the cross-coupled latch is coupled to a gate of the pass transistor which, in turn, is connected between the bit line and the negative voltage supply. When the data signal is in a first logic state, the cross-coupled latch turns on the pass transistor and, in connecting the bit line to the negative voltage supply, facilitates programming of the cell.

Abstract: A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n- well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

Abstract: A charge pump circuit including N stages of diode-capacitor voltage multipliers clocked so as to convert a low voltage received from a supply voltage to a high voltage at an output terminal thereof employs an output stage to improve the efficiency of the charge pump. The output stage includes first and second legs each coupled to the output terminal, where the first leg provides current to the output terminal during low transitions of the clock signal and the second leg provides current to the output terminal during high transitions of the clock signal. In some embodiments, numerous ones of the above-mentioned charge pump circuit may be connected in parallel to achieve even greater output currents. Thus, unlike conventional charge pump circuits, a substantially constant current is provided to the output terminal throughout each period of the clock signal, thereby increasing the average total current provided to the output terminal and, thus, increasing the driving capability of the charge pump circuit.

Abstract: A semiconductor memory includes a plurality of memory cells and a corresponding plurality of page buffers. When writing to a selected row of cells, input data is first latched into the page buffers. The cells in the selected row are then programmed according to the data latched within the page buffers. After programming, data stored in the cells is forwarded to the corresponding page buffers. If, for each cell, the data stored in the cell matches the data latched in its corresponding page buffer, the page buffer is reset. The selected row of cells are subsequently re-programmed, whereby only cells corresponding to those page buffers which have not been reset are re-programmed. In this manner, cells properly programmed during the first program operation are not re-programmed during program verify operations.

Abstract: A device for eliminating low frequency radiation of a computer monitor is disclosed, including a pair of first conductive plates disposed on two opposite sides of a cathode ray tube of the monitor to generate a radiation signal thereon that is induced by the low frequency radiation of the monitor, the radiation signal being applied to a circuit which amplifies and inverts the radiation signal to generate an in inverted and amplified output signal, the output signal being applied to a pair of second conductive plates arranged on another two opposite sides of the cathode ray tube to cancel the low frequency radiation of the cathode ray tube.

Abstract: A sensing circuit charges the bit lines of an associated memory array using one or more large-area pass transistors during reading operations of a selected memory cell of the memory array. In this manner, the read speed of the memory array is independent of the channel current of the memory cell. A sink transistor sinks a constant current from the selected bit line during reading to improve the noise margin of the sensing circuit so that memory arrays associated with the sensing circuit do not require the reference bit lines.

Abstract: A row decoder circuit selectively provides suitable programming, reading, and erasing voltages to an associated memory array employing PMOS floating gate transistors as memory cells. In some embodiments, during programming, the row decoder circuit pulls a selected word line of the associated memory array high to a programming voltage on a first voltage line and maintains an un-selected word line at a predetermined potential. During reading, the row decoder circuit discharges the word line, if selected, to ground potential, and maintains the word line, if un-selected, at a predetermined potential. During erasing, the row decoder circuit charges the word line to a high negative voltage. The row decoder circuit includes isolation means to electrically isolate the word line of the associated memory array from undesirable potentials during programming, reading, and erasing operations.

Abstract: A non-volatile memory latch device includes two PMOS memory cells and a cross-coupled static latch having two PMOS transistors and two NMOS transistors. The floating gates of each PMOS memory cell/transistor pair are coupled together. The control gates of all four PMOS devices are commonly connected to an input. The latch is programmed by applying -3 to -8 volts to the drain of one of the PMOS memory cells, floating the drain of the other PMOS memory cell, and applying 7 to 11 volts to the control gates of all four PMOS devices. The latch is erased by applying 3 to 8 volts to both drains of the PMOS memory cells and -7 to -11 volts to the control gates of all four PMOS devices. Lower programming and erasing voltages are possible with the PMOS latch, as compared with conventional NMOS latches.

Abstract: A row decoder circuit selectively provides suitable programming, reading, and erasing voltages to an associated memory array employing PMOS floating gate transistors as memory cells. In some embodiments, during programming, the row decoder circuit pulls a selected word line of the associated memory array high to a programming voltage on a first voltage line and maintains an un-selected word line at a predetermined potential. During reading, the row decoder circuit discharges the word line, if selected, to ground potential, and maintains the word line, if un-selected, at a predetermined potential. During erasing, the row decoder circuit charges the word line to a high negative voltage. The row decoder circuit includes isolation means to electrically isolate the word line of the associated memory array from undesirable potentials during programming, reading, and erasing operations.

Abstract: A negative voltage level translator includes an output terminal which is electrically connected to a word line of the associated memory array. The voltage level of the output terminal, and thus the voltage level of the associated word line, is controlled by a cross-coupled latch. If the word line associated with the negative voltage level translator has been selected during erasing, the cross-coupled latch enters a first state which results in the output terminal being pulled to a negative erase voltage. This negative erase voltage, which may be generated by a negative charge pump, is in this manner coupled to the control gates of the array's selected memory cells to cause the erasing of such memory cells via, for instance, electron tunneling. If the word line associated with the output terminal has not been selected for erasing, the cross-coupled latch enters a second state which results in the output terminal being maintained at a floating potential.

Abstract: A pulse ramp control circuit allows for the program voltage applied to the control gate of a memory cell to be ramped from a low voltage to a high voltage in a precise manner. The ramp rate of this program voltage is primarily determined by a single capacitor and the bias current provided thereto. By providing a ramped program voltage to the memory array during programming operations, present embodiments effectively cover the entire distribution of program voltage v. program current for the memory cells to be programmed, thereby minimizing over-program and under-program conditions without reducing program time.

Abstract: A charge pump circuit including N stages of diode-capacitor voltage multipliers clocked so as to convert a low voltage received from a supply voltage to a high voltage at an output terminal thereof employs an output stage to improve the efficiency of the charge pump. The output stage includes first and second legs each coupled to the output terminal, where the first leg provides current to the output terminal during low transitions of the clock signal and the second stage provides current to the output terminal during high transitions of the clock signal. In some embodiments, the numerous one of the above-mentioned charge pump circuit may be connected in parallel to achieve even greater output currents. Thus, unlike conventional charge pump circuits, a substantially constant current is provided to the output terminal throughout the period of the clock signal, thereby increasing the average total current provided to the output terminal and, thus, increasing the driving capability of the charge pump circuit.