Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a main branch extending along a first direction on the substrate and a sub-branch extending along a second direction adjacent to the main branch. The semiconductor device also includes a first doped region overlapping the main branch and the sub-branch according to a top view and a second doped region overlapping the first doped region.

Abstract: A method of manufacturing a semiconductor device includes forming a first dielectric layer over a substrate, forming a metal layer in the first dielectric layer, forming an etch stop layer on a surface of the first dielectric layer and the metal layer, removing portions of the metal layer and the etch stop layer to form a recess in the metal layer, and forming a tungsten plug in the recess. The recess is spaced apart from a bottom surface of the etch stop layer.

Abstract: One or more electronic devices that are mounted on a substrate, including at least one cooling plate in contact with the one or more electronic devices, are encapsulated. The substrate is clamped between a first mold half and a second mold half which define a molding cavity for molding the one or more electronic devices. A cavity insert movably located in the first mold half is projected into the cavity in order to contact and apply a sealing pressure onto the at least one cooling plate. After introducing a molding compound into the cavity at a first fill pressure, the molding compound in the cavity is packed by applying a second fill pressure which is higher than the first fill pressure. During this time, the sealing pressure is maintained at values that are higher than the first fill pressure and the second fill pressure.

Abstract: A non-invasive time domain reflection probe calibration method includes: using different volume ratio of ethanol and deionized water mixed solution to calculate a test target's medium weight coefficient and waveguide length of the non-invasive time domain reflection probes; using different concentrations of NaCl solutions to calibrate a waveguide geometric dimensioning of the non-invasive time domain reflection probes; preparing compacted soil samples with known different moisture contents and densities, and calibrating a correlation parameter of compacted soil samples' dielectric constant and conductivity with moisture content and density. The method not only determines the sensitivity of the test target medium of the non-invasive time domain reflection probes, but also obtains the waveguide length and geometric dimensioning of the probe, and realizes an accurate test of moisture content and density of the soil.

Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin, a second fin and a third fin therebetween. A first insulating structure includes a first insulating layer formed between the first and third fins, a capping structure covering the first insulating layer, a first insulating liner covering sidewall surfaces of the first insulating layer and the capping structure and a bottom surface of the first insulating layer, and a second insulating liner formed between the first insulating liner and the first fin and between the first insulating liner and the third fin. The second insulating structure includes a second insulating layer formed between the second fin and the third fin and a third insulating liner formed between the second insulating layer and the second fin and between the second insulating layer and the third fin.

Abstract: A semiconductor structure includes a substrate, a conductive region, a first insulation layer, a second insulation layer, a gate structure, a low-k spacer, a gate contact, and a conductive region contact. The low-k spacer is formed between a sidewall of the gate structure and the first insulation layer. The gate contact is landed on a top surface of the gate structure. A proximity distance between a sidewall of the gate contact and the conductive region contact along a top surface of the second insulation layer is in a range of from about 4 nm to about 7 nm. A method for manufacturing a semiconductor structure is also provided.

Abstract: A semiconductor package includes a chip, a circuit board and a filling material. The circuit board includes a substrate, a patterned metal layer and a protective layer. A circuit area, a chip-mounting area and a flow-guiding area are defined on a surface of the substrate. The chip is mounted on the chip-mounting area. A flow-guiding member of the patterned metal layer is arranged on the flow-guiding area and includes a hollow portion and flow-guiding grooves which are communicated with the hollow portion and arranged radially. The flow-guiding grooves are provided to allow the protective layer to flow toward the hollow portion, and the hollow portion and the flow-guiding grooves are provided to allow the filling material to flow toward the protective layer such that the filling material can cover the protective layer to improve structural strength of the semiconductor package.

Abstract: The present disclosure provides a graphene based dry electrode for electrophysiological readings, in particular for use with EEG, EKG, EMG, and EOG systems and a method for making said electrodes. The electrodes comprising a doped silicon substrate; a silicon carbide film on the substrate; a graphene surface on the silicon carbide film; wherein the graphene surface has undergone a functionalisation and/or intercalation process to increase the amount of oxygen functional groups present, said process being preferably carried out through repeated contact of the graphene surface with an electrolyte solution.

Abstract: A touch panel device includes a face plate, a bracket, and a PCB. The face plate receives a contact. The bracket includes a permanent magnet affixed to a surface of the bracket. The PCB is positioned proximate to the bracket such that a surface of the PCB is adjacent to the bracket. The PCB includes a Hall sensor collocated proximate to the permanent magnet. The touch panel circuit is coupled to the Hall sensor. When the contact is received at the face plate, the PCB moves closer to the bracket. In response, the touch panel circuit receives a voltage from the Hall sensor, determines a force associated with the contact based upon the voltage, and triggers a haptic feedback response in the bracket.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: send, by a battery management unit (BMU) of a battery of an information handling system (IHS), a request for a first amount of current to an embedded controller (EC) of the IHS; provide, by the EC, the request for the first amount of current to a charger of the IHS; receive, by the charger, the request; provide, by the charger, a second amount of current based at least on the request and based at least on a voltage measurement across a resistor of the charger; determine, by the BMU, a measurement of the second amount of current; provide, by the BMU, the measurement to the EC; determine, by the EC, that the measurement does not match the first amount of current; and provide, by the EC, an alert.

Abstract: A method for fabricating a package structure is provided. The method includes premixing cellulose nanofibrils (CNFs) and a two-dimensional (2D) material in a solvent to form a solution; removing the solvent from the solution to form a composite filler; mixing a prepolymeric material with the composite filler to form a composite material; and performing a molding process using the composite material.

Abstract: A touch panel device includes a face plate, a force-feedback device, and a touch panel circuit. The face plate receives at a first surface a contact with the face plate. The force-feedback device includes a PCB affixed by a first surface of the PCB to a second surface of the face plate. The PCB includes a first metallic ring on a second surface of the PCB. The piezo disc includes a piezoelectric wafer and a second metallic ring. The piezo disc is adjacent to the second surface of the PCB. The touch panel circuit is coupled to the first metallic ring, the second metallic ring, and the piezoelectric wafer. The touch panel circuit determines a capacitance between the first metallic ring and the second metallic ring, determines a force associated with the contact based upon the capacitance, and triggers a haptic feedback response in the piezoelectric wafer.

Abstract: A screw boss assembly, including: a plastic substrate, including: a bottom surface including a first channel; an indented surface; a sidewall surface connecting the bottom surface and the indented surface, the sidewall surface including second channels, each of the second channels connected to the first channel; a metal insert, including: a first contacting member; second contacting member; connecting members connecting the first contacting member to the second contacting member; wherein the metal insert is coupled with the plastic substrate such that the first contacting member is positioned within the first channel and the connecting members are positioned within respective second channels.

Abstract: An information handling system motherboard integrates components through integrated wirelines, including at least some components coupled to the motherboard on opposite sides of a narrow region, such as formed by an opening that accepts a cooling fan. A bridge circuit board couples to contacts of the motherboard on opposing sides of the narrow region so that wirelines integrated in the bridge circuit board interface motherboard wirelines, thus offering greater communication density across the narrow region.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: send, by a battery management unit (BMU) of a battery of an information handling system (IHS), a request for a first amount of current to an embedded controller (EC) of the IHS; provide, by the EC, the request for the first amount of current to a charger of the IHS; receive, by the charger, the request; provide, by the charger, a second amount of current based at least on the request and based at least on a voltage measurement across a resistor of the charger; determine, by the BMU, a measurement of the second amount of current; provide, by the BMU, the measurement to the EC; determine, by the EC, that the measurement does not match the first amount of current; and provide, by the EC, an alert.

Abstract: A screw boss assembly, including: a plastic substrate, including: a bottom surface including a first channel; an indented surface; a sidewall surface connecting the bottom surface and the indented surface, the sidewall surface including second channels, each of the second channels connected to the first channel; a metal insert, including: a first contacting member; second contacting member; connecting members connecting the first contacting member to the second contacting member; wherein the metal insert is coupled with the plastic substrate such that the first contacting member is positioned within the first channel and the connecting members are positioned within respective second channels.

Abstract: An information handling system motherboard integrates components through integrated wirelines, including at least some components coupled to the motherboard on opposite sides of a narrow region, such as formed by an opening that accepts a cooling fan. A bridge circuit board couples to contacts of the motherboard on opposing sides of the narrow region so that wirelines integrated in the bridge circuit board interface motherboard wirelines, thus offering greater communication density across the narrow region.

Abstract: An information handling system motherboard integrates components through integrated wirelines, including at least some components coupled to the motherboard on opposite sides of a narrow region, such as formed by an opening that accepts a cooling fan. A bridge circuit board couples to contacts of the motherboard on opposing sides of the narrow region so that wirelines integrated in the bridge circuit board interface motherboard wirelines, thus offering greater communication density across the narrow region.

Abstract: Systems and methods for a hack-proof security keyboard are described. In some embodiments, a keyboard module may include a first circuit configured to detect activation of a plurality of keys and a second circuit configured to detect activation of a subset of the plurality of keys, where the second circuit overlies the first circuit. In other embodiments, a method may include detecting an electrical signal received from a secondary membrane of a keyboard, where the keyboard includes a primary membrane configured to detect individual activation of any of a plurality of keys, and where the secondary membrane is configured to output the electrical signal in response to concurrent activation of a subset of the plurality of keys. The method may also include performing a selected action in response to the detection.