Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dielectric bar having a left sidewall and a right sidewall; a first nanosheet transistor having a first set of channel nanosheets in direct contact with the left sidewall of the dielectric bar; and a second nanosheet transistor having a second set of channel nanosheets in direct contact with the right sidewall of the dielectric bar, where a first portion of the dielectric bar between the first and the second set of channel nanosheets has a first height; a second portion of the dielectric bar between a first source/drain region of the first nanosheet transistor and a second source/drain region of the second nanosheet transistor has a second height; and the first height is higher than the second height. A method of forming the same is also provided.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second dielectric bar each having a left sidewall and a right sidewall; a first set of nanosheets having a first end and a second end that is directly adjacent to the left sidewall of the first dielectric bar; a first conductive layer surrounding the first set of nanosheets and directly adjacent to the left sidewall of the first dielectric bar; a second set of nanosheets having a first end and a second end that is directly adjacent to the left sidewall of the second dielectric bar; and a second conductive layer surrounding the second set of nanosheets; directly adjacent to the left sidewall of the second dielectric bar; and separating the second set of nanosheets from the right sidewall of the first dielectric bar. A method of forming the same is also provided.

Abstract: A method includes forming a first stage of a multi-stage via in a semiconductor structure utilizing processing from a first side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The method also includes forming a second stage of the multi-stage via utilizing processing from a second side of the semiconductor structure, the first stage of the multi-stage via having a first surface and a second surface opposite the first surface. The first surface of the first stage of the multi-stage via is proximate the first side of the semiconductor structure, the first surface of the second stage of the multi-stage via is proximate the second side of the semiconductor structure, and the second surface of the first stage of the multi-stage via abuts the second surface of the second stage of the multi-stage via.

Abstract: A semiconductor structure includes an upper-level CMOS transistor layer having a plurality of upper-level N-type and P-type field effect transistors; and a frontside interconnect layer above, and interconnected with, the upper-level transistor layer. The frontside interconnect layer includes frontside power rails and frontside signal wiring, and at least three frontside interconnect layer metal levels. A lower-level CMOS transistor layer has a plurality of lower-level N-type and P-type field effect transistors; and a backside interconnect layer below, and interconnected with, the lower-level transistor layer. The backside interconnect layer includes backside power rails and backside signal wiring and at least three backside interconnect layer metal levels.

Abstract: A semiconductor device includes a first source/drain region connected to a back end of line (BEOL) through a first contact and a first via, and a second source/drain region connected to the BEOL through a second contact, a lateral contact, and a second via. The first via passes through the lateral contact.

Abstract: A semiconductor device includes a first source/drain region, a first contact over the first source/drain region, a second source/drain region, and a lateral contact connecting the second source/drain region to a back end of line (BEOL). Portions of the first contact are recessed, and the lateral contact overlaps with the recessed portions of the first contact. The first source/drain region is formed over the second source/drain region.

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.

Abstract: A semiconductor device including stacked field effect transistors (FETs) is provided. The stacked FETs are formed utilizing a process that optimizes the thermal budget without negatively impacting the frontside and/or backside contact structures. The stacked can be designed to have different work function metals and a frontside/backside deep via structure can be provided that has a low area resistance.

Abstract: A microelectronic structure includes a first row of stack nano devices that includes a plurality of a first stacked nano FET devices and a second row of stack nano devices that includes a plurality of a second stacked nano FET devices. Each of the plurality of first nano stacked FET devices and each of the plurality of second stacked FET devices includes an upper stack transistor and a lower stack transistor. A gate cut located between the first row of stacked nano devices and the second row stacked nano devices. An interconnect located within gate cut. The interconnect is connected to a source/drain of one of the lower stacked transistors and the interconnect includes a non-uniform backside surface.

Abstract: A transistor includes a gate structure with reduced gate region or eliminated gate region located between a top MDI region and a bottom MDI region. The reduced gate region has a reduction of conductive material therewithin and may be formed due to the presence of prefabricated wide inner spacers between the top MDI region and the bottom MDI region. The no gate region has an absence of conductive material therewithin and may be formed due to the presence of a prefabricated inner spacer that is between, and has a coplanar perimeter with, the top MDI region and the bottom MDI region. By reducing or eliminating the conductive material of the gate structure between the dual MDI structure, parasitic capacitance otherwise associated therewith is reduced.

Abstract: A semiconductor structure includes a first stacked device having a first field-effect transistor containing one or more first nanosheet layers, a second field-effect transistor containing one or more second nanosheet layers; and a first dielectric insulator layer positioned between the first field-effect transistor and the second field-effect transistor, the first dielectric insulator layer having a first width. The semiconductor structure further includes a second stacked device adjacent the first stacked device. The second stacked device having a third field-effect transistor containing one or more third nanosheet layers, a fourth field-effect transistor containing one or more fourth nanosheet layers, and a second dielectric insulator layer positioned between the third field-effect transistor and the fourth field-effect transistor. The second dielectric insulator layer has a second width less than the first width of the first dielectric insulator layer.

Abstract: Embodiments of the present invention are directed to processing methods and resulting structures for providing contacts for gate, source, and drain regions through a wafer backside. In a non-limiting embodiment of the invention, a front end of line structure having a gate and a source or drain (S/D) region is formed and a back end of line structure is formed on a first surface of the front end of line structure. The back end of line structure includes a backside S/D contact on a surface of the S/D region, a backside gate contact on a surface of the gate, and a backside contact liner in direct contact with a sidewall of the backside S/D contact and a sidewall of the backside gate contact. The backside gate contact is electrically isolated from the backside S/D contact by the backside contact liner.

Abstract: Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a PFET source/drain (S/D). The PFET S/D may include a silicon germanium (SiGe)-based epi protruding through a BILD plane between a backside interlayer dielectric (BILD) and a first gate, and an NFET S/D. The NFET S/D may include a silicon (Si)-based epi protruding into the BILD plane and a SiGe epi between the BILD and the Si-based.

Abstract: A semiconductor structure includes logic device and passive device regions. The logic device region includes field effect transistors (FETs) having a gate structure and a source/drain region disposed on opposing sides of the gate structure. At least one source/drain region extends within a buried dielectric layer for electrically connecting a FET to a backside power rail (BPR). The passive device region includes passive devices disposed on a first side of a first semiconductor layer. A second semiconductor layer is disposed above a second side of the first semiconductor layer opposing the first side. A backside interlevel dielectric (BILD) is above the second semiconductor layer and the buried dielectric layer. The BPR is embedded within the BILD in the logic device region. A top surface of the BILD in the passive device region is coplanar with a top surface of the BPR and the BILD in the logic device region.

Abstract: A semiconductor device is provided and includes a first substrate including a first transistor; a laser reflection layer on the first transistor; and a second substrate on the laser reflection layer, the second substrate including a second transistor.

Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.

Abstract: An upper portion of a source/drain epitaxy adjacent to channel layers of a nanosheet stack on a substrate, a lower portion of the source/drain epitaxy below the upper portion of the source/drain epitaxy, a second width of the lower portion of the source/drain epitaxy is greater than a first width of the upper portion of the source/drain epitaxy, a dielectric fill layer below the nanosheet stack, and a dielectric encapsulation liner between the dielectric fill layer and the lower portion of the source/drain epitaxy. Forming an upper portion of a source/drain epitaxy adjacent to semiconductor channel layers of a nanosheet stack, and forming a lower portion of the source/drain epitaxy below the upper portion of the source/drain epitaxy, a second width of the lower portion of the source/drain epitaxy is greater than a first width of the upper portion of the source/drain epitaxy.

Abstract: A neural network device comprises a first plurality of synapse network capacitors, wherein the synapse network capacitors of the first plurality of synapse network capacitors share a first output terminal. The neural network device further comprises a second plurality of synapse network capacitors, wherein the synapse network capacitors of the second plurality of synapse network capacitors share a second output terminal. Still further, the neural network device comprises a metal shielding disposed between the first output terminal and the second output terminal. The neural network device may be used as part of an artificial intelligence system.

Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.