Patents by Inventor Terry Parks

Terry Parks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170301386
    Abstract: A controller for controlling a dynamic random access memory (DRAM) comprising a plurality of blocks. A block is one or more units of storage in the DRAM for which the DRAM controller can selectively enable or disable refreshing. The DRAM controller includes flags each for association with a block of the blocks of the DRAM. A sanitize controller determines a block is to be sanitized and in response sets a flag associated with the block and disables refreshing the block. In response to subsequently receiving a request to read data from a location in the block, if the flag is clear, the DRAM controller reads the location and returns data read from it. If the flag is set, the DRAM controller refrains from reading the DRAM and returns a value of zero.
    Type: Application
    Filed: October 26, 2016
    Publication date: October 19, 2017
    Inventors: TERRY PARKS, RODNEY E. HOOKER, DOUGLAS R. REED
  • Patent number: 9792121
    Abstract: A microprocessor includes an instruction translation unit that extracts condition information from the IT instruction and fuses the IT instruction with the first IT block instruction. For each instruction of the IT block, the instruction translation unit: determines a respective condition for the IT block instruction using the condition information extracted from the IT instruction and translates the IT block instruction into a microinstruction. The microinstruction includes the respective condition. Execution units conditionally execute the microinstruction based on the respective condition. For each IT block instruction, the instruction translation unit determines a respective state value using the extracted condition information. The state value comprises the lower eight bits of the IT instruction having the lower five bits left-shifted by N-1 bits, where N indicates a position of the IT block instruction in the IT block.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: October 17, 2017
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Terry Parks, G. Glenn Henry
  • Patent number: 9792223
    Abstract: A processor including an extended page table (EPT) translation mechanism that is enabled for virtualization, and a load EPT instruction. When executed by the processor, the load EPT instruction directly invokes the EPT translation mechanism to directly convert a provided guest physical address into a corresponding true physical address. The EPT translation mechanism may include an EPT paging structure and an EPT tablewalk engine. The EPT paging structure is generated and stored in an external system memory when the EPT translation mechanism is enabled. The EPT tablewalk engine is configured to access the EPT paging structure for the physical address conversion. The EPT tablewalk engine may perform relevant checks to trigger EPT misconfigurations and EPT violations during execution of the load EPT instruction.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: October 17, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Colin Eddy, Terry Parks
  • Patent number: 9768803
    Abstract: A hardware data compressor that compresses an input block of characters by replacing strings of characters in the input block with back pointers to matching strings earlier in the input block. A hash table is used in searching for the matching strings in the input block. A plurality of hash index generators each employs a different hashing algorithm on an initial portion of the strings of characters to be replaced to generate a respective index. The hardware data compressor also includes an indication of a type of the input block of characters. A selector selects the index generated by of one of the plurality hash index generators to index into the hash table based on the type of the input block.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: September 19, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 9759368
    Abstract: A multipurpose lighting and entertainment stand including a base unit and each of a plurality of vertically disposed telescopic legs and a trash can attached to the base unit. A horizontally disposed platform is disposed directly atop the plurality of vertically disposed telescopic legs. Each of a right opening and a left opening of a pair of circular cup holder openings is disposed through the horizontally disposed platform. A pair of attached identical triangular compartments is disposed on and extended rearward from a rear edge of the horizontally disposed platform. Each of a right hook and a left hook of a pair of hooks is attached to an external surface of the pair of attached identical triangular compartments. A lighting unit having a plurality of upward facing light emitting diodes is disposed on an upper ledge of the pair of attached identical triangular compartments.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 12, 2017
    Inventors: Terry Parks, Esther Parks
  • Patent number: 9727480
    Abstract: A processor includes translation-lookaside buffer (TLB) and a mapping module. The TLB includes a plurality of entries, wherein each entry of the plurality of entries is configured to hold an address translation and a valid bit vector, wherein each bit of the valid bit vector indicates, for a respective address translation context, the address translation is valid if set and invalid if clear. The TLB also includes an invalidation bit vector having bits corresponding to the bits of the valid bit vector of the plurality of entries, wherein a set bit of the invalidation bit vector indicates to simultaneously clear the corresponding bit of the valid bit vector of each entry of the plurality of entries. The mapping module generates the invalidation bit vector.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: August 8, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Terry Parks, Colin Eddy, Viswanath Mohan, John D. Bunda
  • Publication number: 20170161195
    Abstract: A processor including a programmable prefetcher for prefetching information from an external memory. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks load requests issued by the processor to retrieve information from the external memory. The programmable prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The requester uses each generated prefetch address to prefetch information from the external memory. A prefetch memory may store one or more prefetch programs and a prefetch programmer may be included to select from among stored prefetch programs to program the prefetcher based on an executing process. Each prefetch program may be configured according to a prefetch definition.
    Type: Application
    Filed: October 28, 2016
    Publication date: June 8, 2017
    Inventors: G. GLENN HENRY, RODNEY E. HOOKER, TERRY PARKS, DOUGLAS R. REED
  • Publication number: 20170161196
    Abstract: A processor including a front end, at least one load pipeline, and a memory system that further includes a programmable prefetcher for prefetching information from an external memory. The front end converts fetched program instructions into microinstructions including load microinstructions and dispatches microinstructions for execution. The load pipeline executes dispatched load microinstructions and provides load requests to the memory system. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks the load requests. The prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The prefetch requester submits the at least one prefetch address to prefetch information from the memory system.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 8, 2017
    Inventors: G. GLENN HENRY, RODNEY E. HOOKER, TERRY PARKS, DOUGLAS R. REED
  • Publication number: 20170161067
    Abstract: A processor with an expandable instruction set architecture for dynamically configuring execution resources. The processor includes a programmable execution unit (PEU) that may be programmed to perform a user-defined function in response to a user-defined instruction (UDI). The PEU includes programmable logic elements and programmable interconnectors that are collectively programmed to perform at least one processing operation. A UDI loader is responsive to a UDI load instruction that specifies a UDI and a location of programming information that is used to program the PEU. The PEU may be programmed for one or more UDIs for one or more processes. An instruction table stores each UDI and corresponding information to identify the UDI and possibly to reprogram the PEU if necessary. A UDI handler consults the instruction table to identify a received UDI and to send corresponding information to the PEU to execute the corresponding user-defined function.
    Type: Application
    Filed: October 28, 2016
    Publication date: June 8, 2017
    Inventors: G. GLENN HENRY, RODNEY E. HOOKER, TERRY PARKS, DOUGLAS R. REED
  • Publication number: 20170161036
    Abstract: A compiler system that converts an application source program into an executable program according to a predetermined ISA executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The compiler system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for programming the PEU to perform the processing operation in response to the specified UDI. The compiler system includes a compiler that converts the application source program into the executable program, which includes an optimization routine that represents a portion of the application source program with the specified UDI and that inserts the UDI into the executable program, and that further inserts into the executable program a UDI load instruction that specifies the UDI and a location of the programming information in the executable program.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 8, 2017
    Inventors: G. GLENN HENRY, RODNEY E. HOOKER, TERRY PARKS, DOUGLAS R. REED
  • Publication number: 20170161037
    Abstract: A conversion system that converts a standard executable program according to a predetermined ISA into a custom executable program executable by a general purpose processor. The processor includes a PEU that is programmable to execute a UDI. The conversion system includes a PEU programming tool that converts a functional description of a processing operation to be performed by the PEU of the processor into programming information for the PEU to perform the processing operation in response to the UDI. A converter converts the standard executable program into the custom executable program and includes an optimization routine that replaces a portion of the standard executable program with the specified UDI and that inserts the UDI into the custom executable program, and that further inserts a UDI load instruction that specifies the UDI and a location of the programming information in the custom executable program.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 8, 2017
    Inventors: G. GLENN HENRY, RODNEY E. HOOKER, TERRY PARKS, DOUGLAS R. REED
  • Patent number: 9652398
    Abstract: An associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set. Each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. Each valid storage element has an associated MAT; a mapping that includes, for each MAT, a MAT priority. In response to a memory access that misses in the array, the allocation unit: determines a most eligible way and a second most eligible way of the selected set for replacement based on a replacement policy; and replaces the second most eligible way rather than the most eligible way when the MAT priority of the most eligible way is greater than the MAT priority of the second most eligible way.
    Type: Grant
    Filed: December 14, 2014
    Date of Patent: May 16, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Rodney E. Hooker, Douglas R. Reed, John Michael Greer, Colin Eddy, Terry Parks
  • Patent number: 9645822
    Abstract: An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: May 9, 2017
    Assignee: VIA TECHNOLOGIES, INC
    Inventors: G. Glenn Henry, Terry Parks, Rodney E. Hooker, Gerard M. Col, Colin Eddy
  • Patent number: 9628111
    Abstract: A engine of a hardware data compressor maintains first and second hash tables while it scans an input block of characters to be compressed. The first hash table is indexed by a hash of N characters of the input block. The second hash table is indexed by a hash of M characters of the input block. M is greater than two. N is greater than M. The engine uses the first hash table to search the input block behind a current search target location for a match of at least N characters at the current search target location, and uses the second hash table to search the input block behind the current search target location for a match of at least M characters at the current search target location when no match of at least N characters at the current search target location using the first hash table is found.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 18, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: G. Glenn Henry, Terry Parks
  • Publication number: 20170102920
    Abstract: A neural network unit includes a random bit source that generates random bits and a plurality of neural processing units (NPU). Each NPU includes an accumulator into which the NPU accumulates a plurality of products as an accumulated value and a rounder that receives the random bits from the random bit source and stochastically rounds the accumulated value based on a random bit received from the random bit source.
    Type: Application
    Filed: April 5, 2016
    Publication date: April 13, 2017
    Inventors: G. GLENN HENRY, TERRY PARKS
  • Publication number: 20170103303
    Abstract: A neural network unit has at least one RAM, an output buffer and an array of neural processing units that: read first time step context layer node values from the output buffer; read second time step input layer node values from the RAM; generate second time step hidden layer node values based on the read input and context layer node values; output the hidden layer node values to the output buffer rather than to the RAM; read the hidden layer node values from the output buffer; generate second time step context layer node values based on the read hidden layer node values; output the context layer node values to the output buffer rather than to the RAM; generate output layer node values using the hidden layer node values; write the output layer node values to the RAM; and repeat for a sequence of time steps.
    Type: Application
    Filed: April 5, 2016
    Publication date: April 13, 2017
    Inventors: G. GLENN HENRY, TERRY PARKS, KYLE T. O'BRIEN
  • Publication number: 20170103311
    Abstract: A neural network unit has a first memory that holds elements of a data matrix and a second memory that holds elements of a convolution kernel. An array of neural processing units (NPU) each have a multiplexed register that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU. A register receives a corresponding element of a row from the second memory. An arithmetic unit receives the outputs of the register, the multiplexed register and an accumulator and performs a multiply-accumulate operation on them. For each sub-matrix of a plurality of sub-matrices of the data matrix, each arithmetic unit selectively receives either the element from the first memory or the adjacent NPU multiplexed register output and performs a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel.
    Type: Application
    Filed: April 5, 2016
    Publication date: April 13, 2017
    Inventors: G. GLENN HENRY, TERRY PARKS, KYLE T. O'BRIEN
  • Publication number: 20170103321
    Abstract: A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has an ALU, an accumulator, and a reciprocal multiplier unit. The ALU performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and accumulates the sequence of results as an accumulated value into the accumulator. The reciprocal multiplier unit receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor.
    Type: Application
    Filed: April 5, 2016
    Publication date: April 13, 2017
    Inventors: G. GLENN HENRY, TERRY PARKS
  • Publication number: 20170103040
    Abstract: A processor has functional units that fetch and decode architectural instructions of an architectural instruction set at a first rate, a register that stores a value of an indicator programmable by execution of an architectural instruction of the architectural instruction set, and an execution unit. The execution unit includes a first memory that holds data, a second memory that holds instructions of a program, and a plurality of processing units that execute the program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory. The instructions are of an instruction set that is distinct from the architectural instruction set. The second rate is the first rate when the indicator is programmed with a first value and the second rate is less than the first rate when the indicator is programmed with a second value.
    Type: Application
    Filed: April 5, 2016
    Publication date: April 13, 2017
    Inventors: G. GLENN HENRY, TERRY PARKS
  • Publication number: 20170102940
    Abstract: An array of N processing units (PU) each has: an accumulator; an arithmetic unit performs an operation on first, second and third inputs to generate a result to store in the accumulator, the first input receives the accumulator output; a weight input is received by the second input to the arithmetic unit; a multiplexed register has first and second data inputs, an output received by the third input to the arithmetic unit, and a control input that controls the data input selection. The multiplexed register output is also received by an adjacent PU's multiplexed register second data input. The N PU's multiplexed registers collectively operate as an N-word rotater when the control input specifies the second data input. Respective first/second memories hold W/D rows of N weight/data words and provide the N weight/data words to the corresponding weight/multiplexed register first data inputs of the N PUs.
    Type: Application
    Filed: April 5, 2016
    Publication date: April 13, 2017
    Inventors: G. GLENN HENRY, TERRY PARKS