Patents by Inventor Teruaki Chino
Teruaki Chino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9485864Abstract: A bump structure provided on an electrode pad includes a solder member, and a metal layer having a cylindrical portion covering a side surface of the solder member, the metal layer being made of a metal which is higher in melting point than the solder member. An upper part of the cylindrical portion of the metal layer is opened wide.Type: GrantFiled: July 11, 2014Date of Patent: November 1, 2016Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei Imafuji, Katsumi Yamazaki, Noritaka Katagiri, Teruaki Chino
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Patent number: 9380712Abstract: There is provided a wiring substrate. The wiring substrate includes: a wiring pattern of an outermost layer; a solder resist layer having an opening portion therein, wherein a portion of the wiring pattern is exposed through the opening portion, and the exposed portion of the wiring pattern is defined as a connection pad; and a solder bump on the connection pad. The connection pad includes: a solder layer; and a metal post that is entirely covered by the solder layer, wherein a portion of the solder layer is interposed between the connection pad and the metal post.Type: GrantFiled: November 22, 2013Date of Patent: June 28, 2016Assignee: SHINKO ELECTRIC INDSTRIES CO., LTD.Inventor: Teruaki Chino
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Publication number: 20150029689Abstract: A bump structure provided on an electrode pad includes a solder member, and a metal layer having a cylindrical portion covering a side surface of the solder member, the metal layer being made of a metal which is higher in melting point than the solder member. An upper part of the cylindrical portion of the metal layer is opened wide.Type: ApplicationFiled: July 11, 2014Publication date: January 29, 2015Inventors: Kei IMAFUJI, Katsumi YAMAZAKI, Noritaka KATAGIRI, Teruaki CHINO
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Publication number: 20140146503Abstract: There is provided a wiring substrate. The wiring substrate includes: a wiring pattern of an outermost layer; a solder resist layer having an opening portion therein, wherein a portion of the wiring pattern is exposed through the opening portion, and the exposed portion of the wiring pattern is defined as a connection pad; and a solder bump on the connection pad. The connection pad includes: a solder layer; and a metal post that is entirely covered by the solder layer, wherein a portion of the solder layer is interposed between the connection pad and the metal post.Type: ApplicationFiled: November 22, 2013Publication date: May 29, 2014Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Teruaki CHINO
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Patent number: 8610292Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.Type: GrantFiled: November 29, 2012Date of Patent: December 17, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Patent number: 8536715Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.Type: GrantFiled: August 13, 2012Date of Patent: September 17, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Patent number: 8436471Abstract: A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.Type: GrantFiled: July 20, 2010Date of Patent: May 7, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Teruaki Chino, Akihiko Tateiwa, Fumimasa Katagiri
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Patent number: 8431441Abstract: A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package.Type: GrantFiled: April 26, 2011Date of Patent: April 30, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Patent number: 8368235Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.Type: GrantFiled: January 14, 2010Date of Patent: February 5, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Patent number: 8344492Abstract: A first multilayer wiring structure has a first surface and a second surface positioned on an opposite side to the first surface, a first wiring pattern formed on the second surface side and a housing portion penetrating through the first multilayer wiring structure from the first surface to the second surface. An electronic component has an electrode pad. The electronic component is accommodated in the housing portion in a state that an electrode pad formation surface at the side where the electrode pad is formed is positioned on the second surface side of the first multilayer wiring structure. A second multilayer wiring structure has an insulating layer and a second wiring pattern which are stacked on the second surface of the first multilayer wiring structure and the electrode pad formation surface of the electronic component. The second wiring pattern is electrically connected to the first wiring pattern and the electrode pad.Type: GrantFiled: February 9, 2010Date of Patent: January 1, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Patent number: 8334461Abstract: A wiring board adapted for mounting an electronic component has the form of a structure in which a plurality of wiring layers are stacked one on top of another with an insulating layer interposed therebetween and are interconnected through via holes formed in the insulating layers, respectively. A plurality of openings are formed through the structure in a region where a wiring is not formed, extending through the structure in a thickness direction thereof. Further, solder resist layers are formed on the outermost wiring layers, respectively, and exposing pad portions defined in desired locations in the outermost wiring layers.Type: GrantFiled: October 31, 2008Date of Patent: December 18, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuichi Taguchi, Teruaki Chino, Kiyoshi Oi
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Publication number: 20120306100Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.Type: ApplicationFiled: August 13, 2012Publication date: December 6, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Teruaki CHINO
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Patent number: 8293576Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.Type: GrantFiled: October 4, 2010Date of Patent: October 23, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Publication number: 20110272800Abstract: A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package.Type: ApplicationFiled: April 26, 2011Publication date: November 10, 2011Inventor: Teruaki CHINO
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Patent number: 7985629Abstract: A resin sealing method of a semiconductor device, is provided with: providing a semiconductor device on which a dummy dump is formed; providing a support body including an adhesive layer provided on a surface of the support body; forming a recess in the adhesive layer; inserting the dummy bump of the semiconductor device into the recess of the adhesive layer; adhering the semiconductor device to the adhesive layer with the semiconductor device positioned on the support body; setting the supporting body having the semiconductor device in a resin sealing mold; supplying a resin into a cavity of the resin sealing mold; sealing the semiconductor device with the resin on the support body while using the dummy bump to inhibit displacement of the semiconductor device caused by a flow of the resin supplied into the cavity of the resin sealing mold; and removing the support body, the adhesive layer, and the dummy bump from the semiconductor device sealed with the resin.Type: GrantFiled: December 22, 2009Date of Patent: July 26, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventor: Teruaki Chino
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Patent number: 7928557Abstract: In a stacked package in which a plurality of packages having semiconductor elements mounted on substrates are stacked, while being electrically connected together, by use of connection sections, wherein the connection sections are formed from pillar-like members and solder joint sections and the upper package is supported on the lower package by pillar-like members.Type: GrantFiled: December 10, 2007Date of Patent: April 19, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kiyoshi Oi, Teruaki Chino
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Publication number: 20110079913Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.Type: ApplicationFiled: October 4, 2010Publication date: April 7, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Teruaki CHINO
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Publication number: 20110062578Abstract: A semiconductor device includes a semiconductor chip having a connection electrode on a surface side, and a resin substrate sealing a periphery of the semiconductor chip and formed to have a thickness from a back surface of the semiconductor chip to a lower side thereof, and the resin substrate whose lower surface is positioned to a lower side than the back surface of the semiconductor chip. A wiring layer is connected directly to the connection electrode of the semiconductor chip without the intervention of solder.Type: ApplicationFiled: August 16, 2010Publication date: March 17, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Fumimasa KATAGIRI, Teruaki Chino, Akihiko Tateiwa
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Publication number: 20110049726Abstract: A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.Type: ApplicationFiled: July 20, 2010Publication date: March 3, 2011Inventors: Teruaki CHINO, Akihiko Tateiwa, Fumimasa Katagiri
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Publication number: 20100267208Abstract: A component for semiconductor package which has a protective insulating layer on at least one surface of a component body and exposes a conductive material of the component body to an opening part of the protective insulating layer is manufactured by a method including the steps of (a) forming a mask on at least one surface of the component body, (b) forming the protective insulating layer by filling an opening part of the mask with a protective insulating material by a molding method using a metal mold comprising a mold release film, and (c) removing the metal mold and removing the mask. A typical component is a lead frame or a substrate for semiconductor package.Type: ApplicationFiled: June 30, 2010Publication date: October 21, 2010Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kiyoshi Oi, Teruaki Chino