Patents by Inventor Teruaki Chino

Teruaki Chino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9485864
    Abstract: A bump structure provided on an electrode pad includes a solder member, and a metal layer having a cylindrical portion covering a side surface of the solder member, the metal layer being made of a metal which is higher in melting point than the solder member. An upper part of the cylindrical portion of the metal layer is opened wide.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: November 1, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kei Imafuji, Katsumi Yamazaki, Noritaka Katagiri, Teruaki Chino
  • Patent number: 9380712
    Abstract: There is provided a wiring substrate. The wiring substrate includes: a wiring pattern of an outermost layer; a solder resist layer having an opening portion therein, wherein a portion of the wiring pattern is exposed through the opening portion, and the exposed portion of the wiring pattern is defined as a connection pad; and a solder bump on the connection pad. The connection pad includes: a solder layer; and a metal post that is entirely covered by the solder layer, wherein a portion of the solder layer is interposed between the connection pad and the metal post.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: June 28, 2016
    Assignee: SHINKO ELECTRIC INDSTRIES CO., LTD.
    Inventor: Teruaki Chino
  • Publication number: 20150029689
    Abstract: A bump structure provided on an electrode pad includes a solder member, and a metal layer having a cylindrical portion covering a side surface of the solder member, the metal layer being made of a metal which is higher in melting point than the solder member. An upper part of the cylindrical portion of the metal layer is opened wide.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 29, 2015
    Inventors: Kei IMAFUJI, Katsumi YAMAZAKI, Noritaka KATAGIRI, Teruaki CHINO
  • Publication number: 20140146503
    Abstract: There is provided a wiring substrate. The wiring substrate includes: a wiring pattern of an outermost layer; a solder resist layer having an opening portion therein, wherein a portion of the wiring pattern is exposed through the opening portion, and the exposed portion of the wiring pattern is defined as a connection pad; and a solder bump on the connection pad. The connection pad includes: a solder layer; and a metal post that is entirely covered by the solder layer, wherein a portion of the solder layer is interposed between the connection pad and the metal post.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 29, 2014
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Teruaki CHINO
  • Patent number: 8610292
    Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: December 17, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Patent number: 8536715
    Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: September 17, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Patent number: 8436471
    Abstract: A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: May 7, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Teruaki Chino, Akihiko Tateiwa, Fumimasa Katagiri
  • Patent number: 8431441
    Abstract: A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: April 30, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Patent number: 8368235
    Abstract: A resin sealing method of a semiconductor device includes: positioning semiconductor devices at predetermined positions of an adhesive layer formed on a support body and adhering the semiconductor devices thereto, sealing a part of each of the semiconductor devices with resin by curing a first seal resin in a fluidization state so as to fix the semiconductor devices adhered to the predetermined positions of the adhesive layer formed on the support body, setting the semiconductor devices fixed to the predetermined positions of the adhesive layer formed on the support body in a mold and sealing the exposure parts of the semiconductor devices exposed from the first seal resin with a second seal resin, and removing the support body and the adhesive layer from the semiconductor devices sealed with the resin.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: February 5, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Patent number: 8344492
    Abstract: A first multilayer wiring structure has a first surface and a second surface positioned on an opposite side to the first surface, a first wiring pattern formed on the second surface side and a housing portion penetrating through the first multilayer wiring structure from the first surface to the second surface. An electronic component has an electrode pad. The electronic component is accommodated in the housing portion in a state that an electrode pad formation surface at the side where the electrode pad is formed is positioned on the second surface side of the first multilayer wiring structure. A second multilayer wiring structure has an insulating layer and a second wiring pattern which are stacked on the second surface of the first multilayer wiring structure and the electrode pad formation surface of the electronic component. The second wiring pattern is electrically connected to the first wiring pattern and the electrode pad.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: January 1, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Patent number: 8334461
    Abstract: A wiring board adapted for mounting an electronic component has the form of a structure in which a plurality of wiring layers are stacked one on top of another with an insulating layer interposed therebetween and are interconnected through via holes formed in the insulating layers, respectively. A plurality of openings are formed through the structure in a region where a wiring is not formed, extending through the structure in a thickness direction thereof. Further, solder resist layers are formed on the outermost wiring layers, respectively, and exposing pad portions defined in desired locations in the outermost wiring layers.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: December 18, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuichi Taguchi, Teruaki Chino, Kiyoshi Oi
  • Publication number: 20120306100
    Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.
    Type: Application
    Filed: August 13, 2012
    Publication date: December 6, 2012
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Teruaki CHINO
  • Patent number: 8293576
    Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: October 23, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Publication number: 20110272800
    Abstract: A method of manufacturing a semiconductor package includes placing a semiconductor chip in a recess provided on a surface of a supporting body so that a part of the semiconductor chip projects from the recess; forming a resin part on the surface of the supporting body, the resin part encapsulating the projecting part of the semiconductor chip; removing the supporting body; and forming an interconnection structure electrically connected to the semiconductor chip by using the resin part as a part of the base body of the semiconductor package.
    Type: Application
    Filed: April 26, 2011
    Publication date: November 10, 2011
    Inventor: Teruaki CHINO
  • Patent number: 7985629
    Abstract: A resin sealing method of a semiconductor device, is provided with: providing a semiconductor device on which a dummy dump is formed; providing a support body including an adhesive layer provided on a surface of the support body; forming a recess in the adhesive layer; inserting the dummy bump of the semiconductor device into the recess of the adhesive layer; adhering the semiconductor device to the adhesive layer with the semiconductor device positioned on the support body; setting the supporting body having the semiconductor device in a resin sealing mold; supplying a resin into a cavity of the resin sealing mold; sealing the semiconductor device with the resin on the support body while using the dummy bump to inhibit displacement of the semiconductor device caused by a flow of the resin supplied into the cavity of the resin sealing mold; and removing the support body, the adhesive layer, and the dummy bump from the semiconductor device sealed with the resin.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 26, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Teruaki Chino
  • Patent number: 7928557
    Abstract: In a stacked package in which a plurality of packages having semiconductor elements mounted on substrates are stacked, while being electrically connected together, by use of connection sections, wherein the connection sections are formed from pillar-like members and solder joint sections and the upper package is supported on the lower package by pillar-like members.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: April 19, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kiyoshi Oi, Teruaki Chino
  • Publication number: 20110079913
    Abstract: A method of manufacturing a semiconductor device, includes temporarily fixing a semiconductor chip to a supporting member to direct a connection electrode toward the supporting member side, forming an insulating layer for preventing resin-permeation covering the semiconductor chip, on the supporting member and the semiconductor chip, forming a resin substrate sealing a periphery and a back surface side of the semiconductor chip, on the insulating layer, and removing the supporting member to expose the connection electrode of the semiconductor chip. A build-up wiring is connected directly to the connection electrode of the semiconductor chip.
    Type: Application
    Filed: October 4, 2010
    Publication date: April 7, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Teruaki CHINO
  • Publication number: 20110062578
    Abstract: A semiconductor device includes a semiconductor chip having a connection electrode on a surface side, and a resin substrate sealing a periphery of the semiconductor chip and formed to have a thickness from a back surface of the semiconductor chip to a lower side thereof, and the resin substrate whose lower surface is positioned to a lower side than the back surface of the semiconductor chip. A wiring layer is connected directly to the connection electrode of the semiconductor chip without the intervention of solder.
    Type: Application
    Filed: August 16, 2010
    Publication date: March 17, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Fumimasa KATAGIRI, Teruaki Chino, Akihiko Tateiwa
  • Publication number: 20110049726
    Abstract: A semiconductor package includes a semiconductor chip; a resin part configured to cover a side surface of the semiconductor chip; and a wiring structure formed on a circuit forming surface of the semiconductor chip and a surface of the resin part being situated at the same side as the circuit forming surface, the wiring structure being electrically connected to the semiconductor chip, wherein the resin part is formed so as to cover a part of a surface of the semiconductor chip situated at an opposite side to the circuit forming surface of the semiconductor chip.
    Type: Application
    Filed: July 20, 2010
    Publication date: March 3, 2011
    Inventors: Teruaki CHINO, Akihiko Tateiwa, Fumimasa Katagiri
  • Publication number: 20100267208
    Abstract: A component for semiconductor package which has a protective insulating layer on at least one surface of a component body and exposes a conductive material of the component body to an opening part of the protective insulating layer is manufactured by a method including the steps of (a) forming a mask on at least one surface of the component body, (b) forming the protective insulating layer by filling an opening part of the mask with a protective insulating material by a molding method using a metal mold comprising a mold release film, and (c) removing the metal mold and removing the mask. A typical component is a lead frame or a substrate for semiconductor package.
    Type: Application
    Filed: June 30, 2010
    Publication date: October 21, 2010
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Kiyoshi Oi, Teruaki Chino