Abstract: A power transmission device includes a communication module for transmitting and receiving a power transmission packet, which is an information packet related to the settings of the power transmission, and a general packet, which is an information packet other than the power transmission packet, to and from the power reception device; and a power transmission module for performing the power transmission after transmission and reception of the power transmission packet. The communication module receives address information indicating an address configuration of the memory from the power reception device; provides the general packet with address designation indicating a first memory area, and provides the power transmission packet with address designation indicating a second memory area, on the basis of the address information; and transmits the general packet and the power transmission packet having the address designation to the power reception device.

Abstract: A semiconductor device including: a signal source that generates a sine wave signal; an output section that outputs a measurement signal corresponding to the sine wave signal to a test subject via a first electrode; an input section that receives, as an input signal, the measurement signal that has passed through the test subject and been input via a second electrode; a first calculation device that calculates correlation values between the sine wave signal and the input signal; and a second calculation section that, based on the correlation values, calculates a bioelectrical impedance of the test subject.

Abstract: A power reception device includes a communication circuit for transmitting an information packet that includes a status parameter indicating the status of the battery and a request parameter indicating the amount of transmission power and a transmission time; a power reception circuit for receiving power and charging the battery; and a switching circuit for switching between the communication circuit and the power reception circuit, to connect a power reception coil to one of the communication circuit and the power reception circuit. The communication circuit includes determination circuit for determining the voltage of the battery; and a power reception control circuit for setting values corresponding to the voltage of the battery as the status parameter and the request parameter when the voltage of the battery is equal to or higher than a voltage threshold, and for setting fixed values as the parameters when the voltage of the battery is lower than the threshold.

Abstract: A semiconductor device that receives input data synchronized with a first clock signal and generates output data synchronized with a second clock signal, includes a clock delay circuit that generates first and second delay clock signals, first and second synchronized retrieval circuits that respectively retrieve the input data at timings when each of logical values of the second clock signal and second delay clock signal being switched, to respectively obtain first and second retrieved data, and a clock value retrieval circuit that retrieves a value of the first clock signal at timings when the second clock signal and first delay clock signal respectively switch from the first logical value to the second logical value, to respectively output first and second clock values, and an output circuit that outputs, as the output data, the first or second retrieved data, depending on a value of the first and second clock values.

Abstract: A semiconductor device that receives input data synchronized with a first clock signal and generates output data synchronized with a second clock signal, includes a clock delay circuit that generates first and second delay clock signals, first and second synchronized retrieval circuits that respectively retrieve the input data at timings when each of logical values of the second clock signal and second delay clock signal being switched, to respectively obtain first and second retrieved data, and a clock value retrieval circuit that retrieves a value of the first clock signal at timings when the second clock signal and first delay clock signal respectively switch from the first logical value to the second logical value, to respectively output first and second clock values, and an output circuit that outputs, as the output data, the first or second retrieved data, depending on a value of the first and second clock values.

Abstract: A power transmission device includes a communication module for transmitting and receiving a power transmission packet, which is an information packet related to the settings of the power transmission, and a general packet, which is an information packet other than the power transmission packet, to and from the power reception device; and a power transmission module for performing the power transmission after transmission and reception of the power transmission packet. The communication module receives address information indicating an address configuration of the memory from the power reception device; provides the general packet with address designation indicating a first memory area, and provides the power transmission packet with address designation indicating a second memory area, on the basis of the address information; and transmits the general packet and the power transmission packet having the address designation to the power reception device.

Abstract: A power reception device includes a communication circuit for transmitting an information packet that includes a status parameter indicating the status of the battery and a request parameter indicating the amount of transmission power and a transmission time; a power reception circuit for receiving power and charging the battery; and a switching circuit for switching between the communication circuit and the power reception circuit, to connect a power reception coil to one of the communication circuit and the power reception circuit. The communication circuit includes determination circuit for determining the voltage of the battery; and a power reception control circuit for setting values corresponding to the voltage of the battery as the status parameter and the request parameter when the voltage of the battery is equal to or higher than a voltage threshold, and for setting fixed values as the parameters when the voltage of the battery is lower than the threshold.

Abstract: A power management controller for controlling start and stop of a plurality of power supplies is disclosed. Each of the power supplies belongs to one of N rails, in which (N+1) states including a first state where all of the rails are turned off and a (k+1)th state (k=1, 2, . . . N) where a first rail to a kth rail are turned on are specified. The power management controller includes a task list memory, a head address register file, a state indicator, and an event management unit.

Abstract: A power management controller for controlling start and stop of a plurality of power supplies is disclosed. Each of the power supplies belongs to one of N rails, in which (N+1) states including a first state where all of the rails are turned off and a (k+1)th state (k=1, 2, . . . N) where a first rail to a kth rail are turned on are specified. The power management controller includes a task list memory, a head address register file, a state indicator, and an event management unit.

Abstract: A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

Abstract: An information processing device includes: an address converter including a base address register in which address conversion information is stored and a conversion circuit that converts a PCI Express standard bus address of an inputted packet to a non-PCI Express standard bus address; and a packet generator. When first configuration information of a first device that has a device-unique unique address, is connected to a non-PCI Express standard bus and is unaware of the unique address is stored, the packet generator generates an address setting-use configuration write request packet, and when second configuration information including change information for changing the base address register to a base address register of a second device where at least one of an address width and an internal memory address is a device-unique unique value, the packet generator generates a change setting-use configuration write request packet and outputs the generated packet to the address converter.

Abstract: A packet-signaling relay device selectively relays incoming signal packets, and includes a random number generation unit which generates a random number, a delete threshold generation unit which generates a delete threshold based on an objective delete probability, a comparison unit which compares the random number and the delete threshold to generate a comparison result, and a delete determination unit which generates a delete/storage determination result based on the comparison result. The packet-signaling relay device further includes a packet receiving-and-storing unit which is responsive to the comparison result to selectively delete or store incoming signal packets, and a sending unit for sending the signal packets stored in the packet receiving-and-storing unit.

Abstract: A transmission apparatus, a signal sending apparatus, and a signal receiving apparatus, and a transmission method, a signal sending method, and a signal receiving method capable of solving a problem of metastability and suppressing a delay of a signal when sending and receiving apparatuses having different operation clock frequencies send/receive the signal representative of control information, for example. Included are a sending part that operates in synchronization with a first clock having a first period to output a transmission signal having a signal level that is inverted in response to an input of a first pulse signal corresponding to the first period and a receiving part that operates in synchronization with a second clock having a second period to output a second pulse signal corresponding to the second period in response to inversion of a signal level of the transmission signal.

Abstract: An information processing device includes: an address converter including a base address register in which address conversion information is stored and a conversion circuit that converts a PCI Express standard bus address of an inputted packet to a non-PCI Express standard bus address; and a packet generator. When first configuration information of a first device that has a device-unique unique address, is connected to a non-PCI Express standard bus and is unaware of the unique address is stored, the packet generator generates an address setting-use configuration write request packet, and when second configuration information including change information for changing the base address register to a base address register of a second device where at least one of an address width and an internal memory address is a device-unique unique value, the packet generator generates a change setting-use configuration write request packet and outputs the generated packet to the address converter.

Abstract: An FFT operational device includes memory banks, an FFT operational circuit, and an FFT memory control circuit. The memory banks can overwrite pieces of data to specified address locations simultaneously or read out the data from the locations simultaneously. The operational circuit receives operands read out from the banks simultaneously to perform an FFT operation processing on the operands to output operation results simultaneously, and repeats the FFT operation processing a predetermined number of times. The memory control circuit receives the operation results output from the operational circuit simultaneously, and changes the order of the data in such a way that the pieces of data required for the operational circuit in the successive operation processing will be provided simultaneously. The resultant data are overwritten to the memory banks. The operational device thereby performs FFT or IFFT processing on hardware, the storage capacity thus being reduced with operational speed increased.

Abstract: A method for establishing a wireless connection between a first wireless device provided in a computer and a second wireless device, wherein group information that identifies the first wireless device is created and set for the first wireless device. The group information is transmitted to the second wireless device and is set for it. The first wireless device creates identification information that identifies the second wireless device with the group information to set it for the second wireless device. The first wireless device uses both of the group information and identification information to specify the second wireless device.

Abstract: A packet-signaling relay device selectively relays incoming signal packets, and includes a random number generation unit which generates a random number, a delete threshold generation unit which generates a delete threshold based on an objective delete probability, a comparison unit which compares the random number and the delete threshold to generate a comparison result, and a delete determination unit which generates a delete/storage determination result based on the comparison result. The packet-signaling relay device further includes a packet receiving-and-storing unit which is responsive to the comparison result to selectively delete or store incoming signal packets, and a sending unit for sending the signal packets stored in the packet receiving-and-storing unit.

Abstract: Three registers are provided in an input register section and each register stores 8 bytes of input packet data upon performing an encryption process or an authorization value creation process on input packet data. Creation of an authorization value using a first EXOR circuit and an AES circuit is performed on the data stored in the first two registers. Then, encryption is performed on the input packet data using the first EXOR circuit and the AES circuit on the data stored in the last two registers. The encrypted data is stored in the last two registers, then the data in the input register section are shifted by 16 bytes. The 16 bytes of data that are a continuation of the input packet data and are repeatedly stored in the last two registers.

Abstract: The present invention provides an information retrieving apparatus and method each of which stores predetermined information at addresses of a Main Table RAM associated with retrieval key data by substituting data indicative of each specific position of the retrieval key data in retrieval range defining data in which a range targeted for retrieval is defined by setting the retrieval range defining data as information indicative of the data being arbitrary data, with a fixed value defined in advance and performing conversion on the retrieval key data by predetermined hash functions; allows a mask Table to store position information indicative of the specific position; when retrieval key data targeted for retrieval is inputted, reads the position information from the mask Table and reads from the Main Table RAM through a data selector, the information stored at the addresses associated therewith by substituting the data indicative of each specific position indicated by the position information of the retrieval

Abstract: An arithmetic unit includes a memory, an arithmetic logic unit, a register and a combining circuit. The arithmetic logic unit executes a predetermined arithmetic operation with respect to the data read from memory. The register temporarily stores the data read from the memory. The combining circuit selects one of the arithmetic logic unit and the register. The combining circuit replaces a part of the data read from the memory with output data received from the selected one of the arithmetic logic unit and the register.