Patents by Inventor Teruhiro KUWAJIMA

Teruhiro KUWAJIMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11307479
    Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 19, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba
  • Patent number: 11145597
    Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: October 12, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Kuwabara, Yasutaka Nakashiba, Teruhiro Kuwajima
  • Publication number: 20210302801
    Abstract: A semiconductor device includes a first insulating layer, an optical modulator, and a multilayer wiring layer. The optical modulator is formed on the first insulating layer. The multilayer wiring layer is formed on the first insulating layer and including a wiring and a resistive element which are spaced apart from each other. The resistive element is formed without overlapping with the optical modulator in plan view. A material of the resistive element is at least one selected from the group consisting of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and silicon chromium.
    Type: Application
    Filed: March 25, 2020
    Publication date: September 30, 2021
    Inventors: Teruhiro KUWAJIMA, Yasutaka NAKASHIBA
  • Patent number: 10895683
    Abstract: A semiconductor device includes an insulating layer, an optical waveguide formed on the insulating layer, a multilayer wiring layer formed on the insulating layer such that the multilayer wiring layer covers the optical waveguide, and a first inductor formed in the multilayer wiring layer.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba
  • Patent number: 10886213
    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: January 5, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Yasutaka Nakashiba, Akira Matsumoto, Akio Ono, Tetsuya Iida
  • Publication number: 20200365508
    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.
    Type: Application
    Filed: August 4, 2020
    Publication date: November 19, 2020
    Inventors: Teruhiro KUWAJIMA, Yasutaka NAKASHIBA, Akira MATSUMOTO, Akio ONO, Tetsuya IIDA
  • Patent number: 10818813
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoo Nakayama, Shinichi Watanuki, Futoshi Komatsu, Teruhiro Kuwajima, Takashi Ogura, Hiroyuki Okuaki, Shigeaki Shimizu
  • Publication number: 20200043847
    Abstract: A semiconductor device includes a first semiconductor chip on which a first circuit is formed and a second semiconductor chip on which two circuits are formed. In the first semiconductor chip, a first inductor on the transmitting side electrically connected with the first circuit and a second inductor on the receiving side electrically connected with the second circuit via the bonding wire are formed. In plan view, the first inductor and the second inductor are disposed so as not to overlap each other, and are arranged along each other.
    Type: Application
    Filed: July 8, 2019
    Publication date: February 6, 2020
    Inventors: Shinichi KUWABARA, Yasutaka NAKASHIBA, Teruhiro KUWAJIMA
  • Patent number: 10553734
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
  • Patent number: 10355161
    Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
  • Publication number: 20190206789
    Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the cod is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view. Even if such wirings (linear wiring parts) are arranged under the coil, the characteristics (for example, RF characteristics) of the semiconductor device are not deteriorated. In addition, the area of the semiconductor device can be reduced or high integration of elements can be realized by laminating elements (for example, MOM capacitance elements and the like) having the coil and the linear wiring parts.
    Type: Application
    Filed: November 15, 2018
    Publication date: July 4, 2019
    Inventors: Teruhiro KUWAJIMA, Yasutaka NAKASHIBA, Akira MATSUMOTO, Akio ONO, Tetsuya IIDA
  • Publication number: 20190198703
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 27, 2019
    Inventors: Tomoo NAKAYAMA, Shinichi WATANUKI, Futoshi KOMATSU, Teruhiro KUWAJIMA, Takashi OGURA, Hiroyuki OKUAKI, Shigeaki SHIMIZU
  • Patent number: 10290577
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 14, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Akira Matsumoto, Yasutaka Nakashiba, Takashi Iwadare
  • Patent number: 10211352
    Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama, Takashi Ogura, Teruhiro Kuwajima
  • Publication number: 20190006535
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.
    Type: Application
    Filed: May 15, 2018
    Publication date: January 3, 2019
    Inventors: Teruhiro KUWAJIMA, Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA
  • Publication number: 20180294222
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Application
    Filed: June 15, 2018
    Publication date: October 11, 2018
    Inventors: Teruhiro KUWAJIMA, Akira MATSUMOTO, Yasutaka NAKASHIBA, Takashi IWADARE
  • Patent number: 10026689
    Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: July 17, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Akira Matsumoto, Yasutaka Nakashiba, Takashi Iwadare
  • Publication number: 20180138325
    Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.
    Type: Application
    Filed: October 30, 2017
    Publication date: May 17, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA, Takashi OGURA, Teruhiro KUWAJIMA
  • Publication number: 20180083154
    Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 22, 2018
    Inventors: Teruhiro KUWAJIMA, Shinichi WATANUKI, Futoshi KOMATSU, Tomoo NAKAYAMA
  • Publication number: 20170148732
    Abstract: An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate and including a plurality of wiring layers, and a first coil, a second coil, and a third coil which are formed above the semiconductor substrate. In a region located under the first coil and overlapping the first coil in plan view, the second and third coils CL2a and CL2b are disposed. The second and third coils are foamed in the same layer and electrically coupled in series to each other. Each of the second and third coils and the first coil are not coupled to each other via a conductor, but are magnetically coupled to each other.
    Type: Application
    Filed: October 25, 2016
    Publication date: May 25, 2017
    Inventor: Teruhiro KUWAJIMA