Patents by Inventor Terunori Warabisako

Terunori Warabisako has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100193362
    Abstract: In a state where a silicon base material (1) is used as an anode, a fine platinum member (2) is used as a cathode, and an electrolyte solution (4) is arranged between the anode and the cathode, anodic oxidation is performed in constant current mode under the conditions where porous formation mode and electrolytic polishing mode coexist. The platinum member (2) is fitted in the silicon base material (1) with silicon elution, and processes such as hole making, cutting, single-side pressing are performed. Since the silicon base material can be processed at a room temperature with small energy, the crystal quality of the processing surface is not deteriorated. Thus, efficient and highly accurate processing can be performed without using a mechanical method, which consumes much material in conventional processes such as cutting of solar cell silicon base material, and without using laser whose energy unit cost is high, and furthermore, without leaving a crystal damage on a processed surface.
    Type: Application
    Filed: May 9, 2008
    Publication date: August 5, 2010
    Inventors: Terunori Warabisako, Toshikazu Shimada, Nobuyoshi Koshida, Bernard Gelloz, Keiichi Kanehori
  • Patent number: 7485505
    Abstract: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin film with a crystal grown in a horizontal direction, the thin-film transistor having a gate insulating film and a gate electrode over the channel region, wherein a drain edge of the drain region which is adjacent to the channel region is formed in the vicinity of a crystal growth end position.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: February 3, 2009
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yoshiaki Nakazaki, Genshiro Kawachi, Terunori Warabisako, Masakiyo Matsumura
  • Patent number: 7407873
    Abstract: A method of manufacturing a semiconductor device includes irradiating a region to be crystallized of a non-monocrystalline semiconductor film with laser beam modulated by an optical modulator to have light intensity distribution having a minimum light intensity line or minimum light intensity spot to crystallize the region, and heating the crystallized region by irradiating light from a flash lamp onto the crystallized region.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: August 5, 2008
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Hiroki Nakamura, Terunori Warabisako, Masakiyo Matsumura
  • Publication number: 20080044975
    Abstract: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin film with a crystal grown in a horizontal direction, the thin-film transistor having a gate insulating film and a gate electrode over the channel region, wherein a drain edge of the drain region which is adjacent to the channel region is formed in the vicinity of a crystal growth end position.
    Type: Application
    Filed: September 14, 2007
    Publication date: February 21, 2008
    Inventors: Yoshiaki NAKAZAKI, Genshiro Kawachi, Terunori Warabisako, Masakiyo Matsumura
  • Patent number: 7288787
    Abstract: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin film with a crystal grown in a horizontal direction, the thin-film transistor having a gate insulating film and a gate electrode over the channel region, wherein a drain edge of the drain region which is adjacent to the channel region is formed in the vicinity of a crystal growth end position.
    Type: Grant
    Filed: July 3, 2006
    Date of Patent: October 30, 2007
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Yoshiaki Nakazaki, Genshiro Kawachi, Terunori Warabisako, Masakiyo Matsumura
  • Publication number: 20070026619
    Abstract: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin film with a crystal grown in a horizontal direction, the thin-film transistor having a gate insulating film and a gate electrode over the channel region, wherein a drain edge of the drain region which is adjacent to the channel region is formed in the vicinity of a crystal growth end position.
    Type: Application
    Filed: July 3, 2006
    Publication date: February 1, 2007
    Inventors: Yoshiaki NAKAZAKI, Genshiro KAWACHI, Terunori WARABISAKO, Masakiyo MATSUMURA
  • Publication number: 20070023757
    Abstract: The present invention provides a thin-film transistor having a higher mobility for electrons or holes, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. Thus, the present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin film having a crystallization region with a crystal grown in a horizontal direction, the thin-film transistor having a gate insulating film and a gate electrode over the channel region, wherein a drain edge of the drain region which is adjacent to the channel region is formed in the vicinity of a crystal growth end position.
    Type: Application
    Filed: July 3, 2006
    Publication date: February 1, 2007
    Inventors: Yoshiaki Nakazaki, Genshiro Kawachi, Terunori Warabisako, Masakiyo Matsumura
  • Publication number: 20060033104
    Abstract: There is disclosed a thin film transistor having a source region, a channel region, and a drain region in a semiconductor thin film whose crystals have grown in a transverse direction, the thin film transistor having a gate insulating film and a gate electrode in an upper part of the channel region, wherein a channel-region-side edge portion of the drain region or the source region is disposed in such a manner as to be positioned in the vicinity of an end position of lateral growth.
    Type: Application
    Filed: August 5, 2005
    Publication date: February 16, 2006
    Applicant: Advanced LCD Technologies Dev. Ctr. Co., Ltd.
    Inventors: Yoshiaki Nakazaki, Fumiki Nakano, Genshiro Kawachi, Terunori Warabisako, Masayuki Jyumonji, Hiroyuki Ogawa, Masato Hiramatsu, Tomoya Kato
  • Publication number: 20060024981
    Abstract: A method of manufacturing a semiconductor device includes irradiating a region to be crystallized of a non-monocrystalline semiconductor film with laser beam modulated by an optical modulator to have light intensity distribution having a minimum light intensity line or minimum light intensity spot to crystallize the region, and heating the crystallized region by irradiating light from a flash lamp onto the crystallized region.
    Type: Application
    Filed: July 25, 2005
    Publication date: February 2, 2006
    Inventors: Hiroki Nakamura, Terunori Warabisako, Masakiyo Matsumura
  • Patent number: 6323415
    Abstract: A light concentrator photovoltaic module includes a medium having a light receiving plane, a plurality of photovoltaic elements arranged in a spaced relationship with the light receiving plane, and a light reflecting plane for conducting light incident upon the light receiving plane but is not directly received by the photovoltaic elements to the photovoltaic elements.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: November 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Uematsu, Terunori Warabisako, Yoshiaki Yazawa, Yoshinori Miyamura, Ken Tsutsui, Shin-ichi Muramatsu, Hiroyuki Ohtsuka, Junko Minemura
  • Patent number: 6294723
    Abstract: Disclosed is a photovoltaic module including a plurality of concentrators each having a light-incident plane and a reflection plane, and photo detectors. Each photo detector is in contact with one of the concentrators. The module is capable of effectively trapping light and effectively generating power throughout the year even if the module is established such that sunlight at the equinoxes is made incident on the light-incident planes not in a perpendicular manner but instead obliquely, for example, in the case where the module is established in contact with a curved plane of a roof, or the like.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: September 25, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Tsuyoshi Uematsu, Terunori Warabisako, Yoshiaki Yazawa, Yoshinori Miyamura, Ken Tsutsui, Shin-ichi Muramatsu, Hiroyuki Ohtsuka, Junko Minemura
  • Publication number: 20010008144
    Abstract: Disclosed is a photovoltaic module including a plurality of concentrators each having a light-incident plane and a reflection plane, and photo detectors each being in contact with one of the concentrators, which is capable of effectively trapping light and effectively generating power throughout the year even if the module is established such that sunlight at the equinoxes is made incident on the light-incident planes not perpendicularly but obliquely from the right, upper side, for example, in the case where the module is established in contact with a curved plane of a roof or the like.
    Type: Application
    Filed: February 23, 1999
    Publication date: July 19, 2001
    Inventors: TSUYOSHI UEMATSU, TERUNORI WARABISAKO, YOSHIAKI YAZAWA, YOSHINORI MIYAMURA, KEN TSUTSUI, SHIN-ICHI MURAMATSU, HIROYUKI OHTSUKA, JUNKO MINEMURA
  • Patent number: 5747864
    Abstract: A light receiving element having excellent characteristics, including high sensitivity and high response speed, can be achieved by a light element comprising unit structures each having two pn junction semiconductor layers, and a lightly doped semiconductor layer having low impurity density, lower than those of the p-type regions and the n-type regions of the two pn junction semiconductor layers, and which is sandwiched between the two pn junction semiconductor layers. The p-type regions of the pn junction semiconductor layers are disposed opposite to each other on opposite sides of the lightly doped semiconductor layer, respectively, and the n-type regions of the pn junction semiconductor layers are disposed opposite to each other on the opposite sides of the lightly doped semiconductor layer, respectively.
    Type: Grant
    Filed: July 31, 1996
    Date of Patent: May 5, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Kitatani, Yoshiaki Yazawa, Junko Minemura, Akira Sato, Terunori Warabisako
  • Patent number: 5064520
    Abstract: This invention relates to a method and an apparatus for forming a film, which are suitable for forming a film of a semiconductor, dielectric, metal, insulator, or organic substance. In order to form a film of high purity and quality at high speed, a particle beam such as an ion beam, an electron beam, or a plasma is applied to a sputtering target comprising a substance formed by bonding atoms or molecules with either van der Waals forces or hydrogen bonding forces, the particles are sputtered thereby from the target, fly in the space in the vacuum chamber, reach the substrate on which they are deposited to form a desired film.
    Type: Grant
    Filed: February 14, 1990
    Date of Patent: November 12, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoshi Miyake, Yasunori Ohno, Masato Isogai, Yukio Nakagawa, Takayoshi Seki, Koukichi Ouhata, Kenichi Natsui, Terunori Warabisako, Keiji Arimatsu
  • Patent number: 4984038
    Abstract: The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.
    Type: Grant
    Filed: May 17, 1988
    Date of Patent: January 8, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Makoto Ohkura, Masanobu Miyao, Kikuo Kusukawa, Masahiro Moniwa, ShinIchiro Kimura, Terunori Warabisako, Tokuo Kure
  • Patent number: 4937641
    Abstract: The side wall part of a recess dug in a Si substrate is used as the major part of the electrode surface of a capacitor, whereby the electrode area is enlarged without enlarging a plane area. Thus, a desired capacitor capacitance can be attained without increasing the breakdown of an insulator film ascribable to the conventional approach of thinning of the insulator film. In addition, a vertical switching transistor is formed on the Si substrate, whereby the Si substrate can be entirely utilized for the formation of the capacitor.
    Type: Grant
    Filed: August 3, 1987
    Date of Patent: June 26, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Makoto Ohkura, Masanobu Miyao, Kikuo Kusukawa, Masahiro Moniwa, ShinIchiro Kimura, Terunori Warabisako, Tokuo Kure
  • Patent number: 4808546
    Abstract: Of an amorphous Si film, a region to be formed into a lowly doped region such as the channel region of an MOS transistor is covered with a mask and an uncovered region is doped with an impurity. After this, the amorphous Si film is annealed and turned to signal crystal through solid phase epitaxial growth, and the mask itself is used as the electrode of a semiconductor device. By this impurity doping, a large-sized single-crystal Si film can be formed, and the impurity doping can be conducted in self-alignment with the electrode formation to produce a highly integrated semiconductor circuit.
    Type: Grant
    Filed: February 2, 1987
    Date of Patent: February 28, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Moniwa, Masanobu Miyao, Shoji Shukuri, Eiichi Murakami, Terunori Warabisako, Masao Tamura, Nobuyoshi Natsuaki, Kiyonori Ohyu, Tadashi Suzuki, Yuuichi Madokoro, Yasuo Wada
  • Patent number: 4768076
    Abstract: A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.At low temperatures, dependency of the carrier mobility upon the plane azimuth becomes more conspicuous as shown in FIG. 1, and the difference of mobility is amplified depending upon the planes. Therefore, employment of the above-mentioned crystalline planes helps produce a great effect when the CMOS device is to be operated at low temperature (e.g., 100.degree. K. or lower), and helps operate the device at high speeds.
    Type: Grant
    Filed: September 11, 1985
    Date of Patent: August 30, 1988
    Assignee: Hitachi, Ltd.
    Inventors: Masaaki Aoki, Toshiaki Masuhara, Terunori Warabisako, Shoji Hanamura, Yoshio Sakai, Seiichi Isomae, Satoshi Meguro, Shuji Ikeda
  • Patent number: 4695856
    Abstract: A semiconductor device, and more particularly a technique for forming the substrate thereof, is provided for the purpose of preventing the occurrence of crystal devects during recrystallization. To accomplish this, while the surface of an insulator on which a material to be recrystallized is flattened, a semiconductor layer which is employed for another use, e.g., the interconnection between elements or the gate electrode of a MOS transistor, is disposed in the insulator. Owing to the flattened insulator, the occurrence of the crystal defects in the recrystallization of the material can be prevented.
    Type: Grant
    Filed: August 20, 1984
    Date of Patent: September 22, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Terunori Warabisako, Makoto Ohkura, Masanobu Miyao
  • Patent number: 4692994
    Abstract: A process for manufacturing semiconductor devices, comprising steps for obtaining a multilayered structure consisting of semiconductors and insulating films, by forming a microbridge which consists of a semiconductor in the form of a connecting bar or a one-side supported bar, and by forming an insulating film by oxidizing the exposed surface of the microbridge. The semiconductor device manufactured by the process of the invention exhibits good interface properties between the insulating film and the semiconductor layer. The invention makes it possible to easily manufacture a variety of MOSFETs with the SOI structure, which exhibit excellent characteristics.
    Type: Grant
    Filed: April 29, 1986
    Date of Patent: September 15, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Moniwa, Terunori Warabisako, Hideo Sunami