Abstract: A method and apparatus for bus expansion, which provides a capability of transferring a data word from a first unit connected to a system bus to a second unit connected to an extension bus, with the first unit receiving a first read request input via the system bus, reading out the data word associated with the first read request, generating a first response in response to reading of the data word, and outputting the first response and the data word onto the system bus, and the second unit generating a second read request in response to an output start command supplied from a central processing unit (CPU) via the extension bus and receiving a second response and a data word from the extension bus. Responsive to the output start command supplied from the CPU, the first read request is selectively generated and output onto the system bus prior to generation of the second read request associated with the first read request.

Abstract: In a computer system, a board voltage reading circuit or a board voltage setting circuit is formed on a board, to effectively read and set the power voltage of the board carrying various types of circuit elements. Board identification number data and board voltage reading mode data are entered into the board voltage reading circuit, and the board voltage setting data is entered into the board voltage setting circuit. These data are entered through a support processor by a display in a console. Only when the board identification number input from support processor and board identification number preset are in agreement each other, the board voltage is read by the board voltage readig circuit. The result is displayed by the display. The board voltage setting circuit is used for setting the power voltage of the board.

Abstract: A cache memory control apparatus according to the present invention includes data register blocks which are individually controlled for each byte, cache memory blocks, and a decoder for generating control signals which control the access to those blocks. In this cache memory control apparatus, when a cache hit is made in a write mode for byte data, the control signal is supplied to the data register blocks and cache memory blocks to individually control the respective blocks, thereby allowing word data corresponding to the write byte data to be synthesized. Thus, the word data can be output to an external device by one operation.