Abstract: A quantum device includes a transistor structure section having a source, a drain, and a gate, one or more quantum dot structure sections in which a charge is localizable, and a quantum bit control current line configured to change a state of the charge in the quantum dot structure section.

Abstract: According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.

Abstract: According to an embodiment, a quantum annealing apparatus includes: an output unit acquiring and outputting components in a Z axis from a plurality of quantum bits in a quantum calculation; and an operation unit executes: a selecting process of selecting a first quantum bit, a second quantum bit and a third quantum bit, the second quantum bit and the third quantum bit being coupled in the quantum calculation unit; a first rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a first axis perpendicular to the Z axis; an interaction operation of causing the first quantum bit and the second quantum bit to interact with each other; and a second rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a second axis perpendicular to the Z axis and the first axis.

Abstract: According to an embodiment, a multiplier accumulator includes a controller, a high-order multiplier, a high-order accumulator, a low-order multiplier, and an output unit. The controller is configured to designate each digit within a range of the most significant digit in a coefficient for an input value to a stop digit as a target digit. The high-order multiplier is configured to calculate a high-order multiplication value by multiplying the input value, and a value and a weight of the target digit. The high-order accumulator is configured to calculate a high-order accumulation value by accumulatively adding the high-order multiplication values for input values. The low-order multiplier is configured to calculate a low-order multiplication value by multiplying an input value and a value of a digit smaller than the stop digit. The output unit is configured to output a value determined based on whether the high-order accumulation value exceeds a boundary value.

Abstract: According to an embodiment, a neural network apparatus includes a plurality of neuron circuits, each including an integration circuit, a firing circuit, and a secondary battery. The integration circuit is configured to output an integral signal obtained by integrating input signals. The firing circuit is configured to generate, in accordance with the integral signal, a pulse signal to be transmitted to the neuron circuit provided at a subsequent layer. The secondary battery is configured to supply the firing circuit with drive electric power used for generating the pulse signal.

Abstract: According to an embodiment, a quantum annealing apparatus includes: an output unit acquiring and outputting components in a Z axis from a plurality of quantum bits in a quantum calculation; and an operation unit executes: a selecting process of selecting a first quantum bit, a second quantum bit and a third quantum bit, the second quantum bit and the third quantum bit being coupled in the quantum calculation unit; a first rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a first axis perpendicular to the Z axis; an interaction operation of causing the first quantum bit and the second quantum bit to interact with each other; and a second rotating operation of rotating each of the second quantum bit and the third quantum bit by 90° around a second axis perpendicular to the Z axis and the first axis.

Abstract: A cache memory has a data cache to store data per cache line, a tag to store address information of the data to be stored in the data cache, a cache controller to determine whether an address by an access request of a processor meets the address information stored in the tag and to control access to the data cache and the tag, and a write period controller to control a period required for writing data in the data cache based on at least one of an occurrence frequency of read errors to data stored in the data cache and a degree of reduction in performance of the processor due to delay in reading the data stored in the data cache.

Abstract: According to one embodiment, a random number generator includes a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal, a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal, a third circuit which outputs a control signal on the basis of the values, and a fourth circuit which controls the first circuit on the basis of the control signal.

Abstract: A data generation apparatus according to an embodiment comprises a memory space including a plurality of memory cells, each including a resistance change element, a first circuit configured to supply the memory cells included in a first space that represents part of the memory space with a current or a voltage that causes a dielectric breakdown to occur in the resistance change element, a second circuit configured to output a value read from the memory cells included in the first space, and an ID generation circuit configured to generate an ID using the value output from the second circuit.

Abstract: An authentication server according to embodiments performs statistical processing on a plurality of pieces of ID data acquired from an electronic device including a PUF circuit generating the pieces of ID data (S1052 to S1071), determines whether the plurality of pieces of ID data are physical random numbers based on a result of the statistical processing (S1072), and when the plurality of pieces of ID data are determined to be physical random numbers, recognizes the result of authentication of the electronic device as a success of authentication (S1073), and when the plurality of pieces of ID data are determined not to be physical random numbers, recognizes a result of authentication of the electronic device as a failure of authentication (S1074).

Abstract: According to one embodiment, a quantum annealing machine 1 includes a quantum bit array 21 which includes a plurality of cells (quantum bits) 211 respectively including a floating gate 105, and a controller 10 which executes writing of data in the plurality of cells 211, and temporally controls tunneling of an electric charge with respect to the floating gate 105.

Abstract: According to an emboediment, a multiplier accumurator includes a controller, a high-order multiplier, a high-order accumulator, a low-order multiplier, and an output unit. The controller is configured to designate each digit within a range of the most significant digit in a coefficient for an input value to a stop digit as a target digit. The high-order multiplier is configured to calculate a high-order multiplication value by multiplying the input value, and a value and a weight of the target digit. The high-order accumulator is configured to calculate a high-order accumulation value by accumulatively adding the high-order multiplication values for input values. The low-order multiplier is configured to calculate a low-order multiplication value by multiplying an input value and a value of a digit smaller than the stop digit. The output unit is configured to output a value determined based on whether the high-order accumulation value exceeds a boundary value.

Abstract: An individual identification device (1) according to embodiments may identify a storage device (100) including one or more memory chips (40). The device comprises a first storage (40), a region allocator (15), and a hardware fingerprint generator (12). The first storage may be configured to store write data. The region allocator may be configured to write the write data in a specific region in each memory chip. The hardware fingerprint generator may be configured to generate hardware fingerprint data based on mismatch bits between the write data and read data read out from the specific region in each memory chip.

Abstract: An authentication server according to embodiments performs statistical processing on a plurality of pieces of ID data acquired from an electronic device including a PUF circuit generating the pieces of ID data (S1052 to S1071), determines whether the plurality of pieces of ID data are physical random numbers based on a result of the statistical processing (S1072), and when the plurality of pieces of ID data are determined to be physical random numbers, recognizes the result of authentication of the electronic device as a success of authentication (S1073), and when the plurality of pieces of ID data are determined not to be physical random numbers, recognizes a result of authentication of the electronic device as a failure of authentication (S1074).

Abstract: According to an embodiment, an authentication system includes a physical device, a calculator, and an authenticator. The physical device includes a data source which outputs a data sequence along time series. The calculator performs, using hidden Markov model, probability calculation on an ID which is based on the data sequence obtained from the physical device. The authenticator authenticates the physical device based on calculation result of the calculator.

Abstract: According to an embodiment, an information processing system includes a time constant processor and a pattern generator. The time constant processor binarizes values indicating a plurality of unit circuits each including a gate insulating film on the basis of a time to emission indicating a time from when a defect in the gate insulating film captures a carrier in a channel current caused to flow by application of a gate voltage to the unit circuits to when the defect emits the carrier. The pattern generator generates a pattern unique to the unit circuits using the values indicating the respective unit circuits binarized by the time constant processor.

Abstract: According to one embodiment, a random number generator includes a first circuit which outputs a second oscillation signal having a predetermined duty ratio on the basis of a first oscillation signal, a second circuit which latches values on the basis of the second oscillation signal and a clock having a frequency lower than a frequency of the second oscillation signal, a third circuit which outputs a control signal on the basis of the values, and a fourth circuit which controls the first circuit on the basis of the control signal.

Abstract: A data generation apparatus according to an embodiment comprises a memory space including a plurality of memory cells, each including a resistance change element, a first circuit configured to supply the memory cells included in a first space that represents part of the memory space with a current or a voltage that causes a dielectric breakdown to occur in the resistance change element, a second circuit configured to output a value read from the memory cells included in the first space, and an ID generation circuit configured to generate an ID using the value output from the second circuit.

Abstract: A data generating device according to embodiments comprises a ring oscillator, a flip-flop circuit and a generator. The flip-flop circuit includes a first terminal and a second terminal to each of which the ring oscillator output is inputted, and that determines a value of output of the ring oscillator. The generator generates an ID for authentication based on one or more values determined by the flip-flop circuit at the time when the ring oscillator is turned on.

Abstract: A magnetic memory includes a magnetoresistive device and a load resistance unit. The magnetoresistive device has a first resistance state and a second resistance state and includes a first ferromagnetic layer and a second ferromagnetic layer. The load resistance unit is electrically connected to the magnetoresistive device. The load resistance unit is in a first state and a second state. Differential resistance of the load resistance unit at the second state is lower than differential resistance of the load resistance unit at the first state.