Abstract: In an optical transmitter having an electro-optic modulator with first child MZI and a second child MZI nested to form a parent MZI, and a processor that controls the bias voltages of electro-optic modulator. In the first section of a control loop, the processor simultaneously superimposes different dither signals onto the first bias voltage of the first child MZI and the second bias voltage of the second child MZI, and extracts the first phase error information for the first child MZI and the first-round third phase error for the parent MZI from a first monitoring result. In the second section of the control loop, the processor simultaneously superimposes different dither signals onto the first and second bias voltages, and extracts the second phase error information for the second child MZI and the second-round third phase error for the parent MZI from a second monitoring result.

Abstract: An optical coherent transceiver includes a transmitter and a receiver that share laser light. The transmitter includes a pair of parent MZIs in a modulator, which are parent MZIs configured to perform quadrature modulation on the laser light according to a bias voltage, and two pairs of child MZIs in the modulator, which are child MZIs configured to perform phase modulation on the laser light according to the bias voltage. The transmitter includes a control circuit configured to control the bias voltage to be applied to the parent MZIs and the child MZIs. The control circuit is configured to, when turning light output of the transmitter off, with input of a data signal being set off, control the bias voltage such that a phase difference between the parent MZIs is around 90 degrees and a phase difference between the child MZIs in each of the pairs is 180 degrees.

Abstract: In an optical transmitter having an electro-optic modulator with first child MZI and a second child MZI nested to form a parent MZI, and a processor that controls the bias voltages of electro-optic modulator. In the first section of a control loop, the processor simultaneously superimposes different dither signals onto the first bias voltage of the first child MZI and 1.0 the second bias voltage of the second child MZI, and extracts the first phase error information for the first child MZI and the first-round third phase error for the parent MZI from a first monitoring result. In the second section of the control loop, the processor simultaneously superimposes different dither signals onto the first and second bias voltages, and extracts the second phase error information for the second child MZI and the second-round third phase error for the parent MZI from a second monitoring result.

Abstract: Controller and control method are provided. In particular, a controller is disclosed as being configured to hold intensities of a monitor signal, which changes according to an output from a region in a device, before and after altering a state of a portion in the region and control the state of the portion based on a difference between the held intensities.

Abstract: Controller and control method are provided. In particular, a controller is disclosed as being configured to hold intensities of a monitor signal, which changes according to an output from a region in a device, before and after altering a state of a portion in the region and control the state of the portion based on a difference between the held intensities.

Abstract: A data receiver circuit includes: a clock/data recovery circuit to recover a clock and data from a received signal; a fixed pattern generation circuit to generate fixed pattern data; a first selection circuit to select and output one of the fixed pattern data generated by the fixed pattern generation circuit and recovered data recovered by the clock/data recovery circuit; a second selection circuit to select and output one of a reference clock and recovered clock recovered by the clock/data recovery circuit; and a switching circuit to make the first selection circuit output the fixed pattern data and to make the second selection circuit output the reference clock, when an input signal is lost or the clock/data recovery circuit is in a loss-of-lock state.

Abstract: There is provided a parallel-serial converter including a selector to convert parallel data to serial data, a flip-flop to which the serial data are input so as to latch the serial data, a generator to generate replica data simulating the serial data, a detector to detect a first switching point of the replica data and a second switching point subsequent to the first switching point, and a controller to control relative timings of timing converted to the serial data in the selector and timing when the serial data is latched in the flip-flop, based on the first switching point and the second switching point.

Abstract: In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value specifies a control voltage-to-oscillation frequency correspondence relation whose upper and lower limits of oscillation frequency are highest, and if the control signal indicates a low level when the controlling value specifies a correspondence relation whose upper and lower limits of oscillation frequency are lowest, the controller outputs a predetermined controlling value. An oscillator has the correspondence relations set therein such that the correspondence relations have respective different upper and lower limits of oscillation frequency and are correlated with the respective controlling values.

Abstract: A data receiver circuit includes: a clock/data recovery circuit to recover a clock and data from a received signal; a fixed pattern generation circuit to generate fixed pattern data; a first selection circuit to select and output one of the fixed pattern data generated by the fixed pattern generation circuit and recovered data recovered by the clock/data recovery circuit; a second selection circuit to select and output one of a reference clock and recovered clock recovered by the clock/data recovery circuit; and a switching circuit to make the first selection circuit output the fixed pattern data and to make the second selection circuit output the reference clock, when an input signal is lost or the clock/data recovery circuit is in a loss-of-lock state.

Abstract: On an optical access network, transmission at different bit rates is realized without modifying subscriber units. A low-speed signal generating part generates a low-speed signal having a low bit rate. A high-speed signal generating part generates a high-speed signal having a high bit rate. A recovery signal generating part generates a recovery signal. A multiplex part generates and sends a multiplexed signal obtained by multiplexing the low-speed signal, the high-speed signal, and the recovery signal. A reception processing part performs processing for receiving the multiplexed signal by extracting clocks from the low-bit-rate signal. When the reception processing part enters a free running state in response to receiving the high-speed signal, the recovery signal generating part generates the recovery signal at a low bit rate in order to recover clock synchronization from the free running state.

Abstract: A signal detecting apparatus detects a signal received based on a current received and includes a detecting unit that detects, in the current received, a peak equal to or higher than a threshold and a time counting unit that counts a given period of time from a point in time of detection of the peak by the detecting unit. The signal detecting apparatus further includes a determining unit that determines whether the detecting unit has detected the peak again within the given period of time counted by the time counting unit. An output unit of the signal detecting apparatus outputs information indicating detection of the signal received when the determining unit determines that the peak has been detected again.

Abstract: In a PLL circuit, a threshold discriminator generates a control signal indicating a relative level of a control voltage. A controller outputs a controlling value based on the control signal. If the control signal indicates a high level when the controlling value specifies a control voltage-to-oscillation frequency correspondence relation whose upper and lower limits of oscillation frequency are highest, and if the control signal indicates a low level when the controlling value specifies a correspondence relation whose upper and lower limits of oscillation frequency are lowest, the controller outputs a predetermined controlling value. An oscillator has the correspondence relations set therein such that the correspondence relations have respective different upper and lower limits of oscillation frequency and are correlated with the respective controlling values.

Abstract: There is provided a parallel-serial converter including a selector to convert parallel data to serial data, a flip-flop to which the serial data are input so as to latch the serial data, a generator to generate replica data simulating the serial data, a detector to detect a first switching point of the replica data and a second switching point subsequent to the first switching point, and a controller to control relative timings of timing converted to the serial data in the selector and timing when the serial data is latched in the flip-flop, based on the first switching point and the second switching point.

Abstract: An optical receiver includes: a converting unit that converts an optical signal into an electrical signal; an amplifying unit that amplifies the electrical signal; a regenerating unit that regenerates the amplified electrical signal; a correcting unit that performs correction of an error included in the regenerated electrical signal; a monitoring unit that performs monitoring of an optical current flowing through the converting unit; and a control unit that calculates a decision threshold based on a result of the correction and a result of the monitoring.

Abstract: In an optical telecommunication system in which an intensity of an arriving optical signal is different for each packet, detected is an optical intensity for each packet with little error. For this purpose, contrived is to detect an average optical intensity across header parts for each packet by focusing on the fact that the header part comprising the preamble and delimiter of a packet is in a bit pattern which includes approximately the same numbers of “0” and “1”.

Abstract: A signal detecting apparatus detects a signal received based on a current received and includes a detecting unit that detects, in the current received, a peak equal to or higher than a threshold and a time counting unit that counts a given period of time from a point in time of detection of the peak by the detecting unit. The signal detecting apparatus further includes a determining unit that determines whether the detecting unit has detected the peak again within the given period of time counted by the time counting unit. An output unit of the signal detecting apparatus outputs information indicating detection of the signal received when the determining unit determines that the peak has been detected again.

Abstract: An optical receiver includes: a converting unit that converts an optical signal into an electrical signal; an amplifying unit that amplifies the electrical signal; a regenerating unit that regenerates the amplified electrical signal; a correcting unit that performs correction of an error included in the regenerated electrical signal; a monitoring unit that performs monitoring of an optical current flowing through the converting unit; and a control unit that calculates a decision threshold based on a result of the correction and a result of the monitoring.

Abstract: On an optical access network, transmission at different bit rates is realized without modifying subscriber units. A low-speed signal generating part generates a low-speed signal having a low bit rate. A high-speed signal generating part generates a high-speed signal having a high bit rate. A recovery signal generating part generates a recovery signal. A multiplex part generates and sends a multiplexed signal obtained by multiplexing the low-speed signal, the high-speed signal, and the recovery signal. A reception processing part performs processing for receiving the multiplexed signal by extracting clocks from the low-bit-rate signal. When the reception processing part enters a free running state in response to receiving the high-speed signal, the recovery signal generating part generates the recovery signal at a low bit rate in order to recover clock synchronization from the free running state.

Abstract: An object of the invention is to provide a control apparatus and a control method having a simple constitution, which can stably perform switching of optical path in an optical signal exchanger, while suppressing an influence on a control due to the mechanical resonance of tilt mirrors. To this end, the control apparatus of the optical signal exchanger is constituted such that in an optical signal exchanger of three-dimensional type using one set of MEMS mirror arrays, each having a plurality of tilt mirrors arranged on a plane, each tilt mirror having a reflecting surface an angle of which is controllable, when the angle of the MEMS mirror on the optical path is feedback controlled by detecting power of an optical signal output from a specific position, a resonance component removing section that removes a resonance frequency component included in a control signal is shared corresponding to a pair of driving electrodes arranged in a coaxial direction of the MEMS mirror.

Abstract: In an optical telecommunication system in which an intensity of an arriving optical signal is different for each packet, detected is an optical intensity for each packet with little error. For this purpose, contrived is to detect an average optical intensity across header parts for each packet by focusing on the fact that the header part comprising the preamble and delimiter of a packet is in a bit pattern which includes approximately the same numbers of “0” and “1”.