Patents by Inventor Tetsuo Ashizawa

Tetsuo Ashizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10121556
    Abstract: A memory circuit with a built-in memory BIST circuit is created by: arranging a block of a clock pulse generator and a plurality of blocks of input/output circuits each corresponding to each of inputted/outputted bits adjacently in a first direction; arranging a block of a BIST pattern generator of the memory BIST circuit which is laid out so that signal wiring is connected by being arranged adjacently and performs generation of a test pattern, adjacently to the block of the clock pulse generator in a second direction; and arranging a plurality of blocks of comparators of the memory BIST circuit which are laid out so that signal wirings are connected by being arranged adjacently and compare an output value and an expected value, adjacently to the plurality of blocks of the input/output circuits in the second direction with the same pitch as that of the input/output circuits.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 6, 2018
    Assignee: SOCIONEXT INC.
    Inventor: Tetsuo Ashizawa
  • Publication number: 20160225464
    Abstract: A memory circuit with a built-in memory BIST circuit is created by: arranging a block of a clock pulse generator and a plurality of blocks of input/output circuits each corresponding to each of inputted/outputted bits adjacently in a first direction; arranging a block of a BIST pattern generator of the memory BIST circuit which is laid out so that signal wiring is connected by being arranged adjacently and performs generation of a test pattern, adjacently to the block of the clock pulse generator in a second direction; and arranging a plurality of blocks of comparators of the memory BIST circuit which are laid out so that signal wirings are connected by being arranged adjacently and compare an output value and an expected value, adjacently to the plurality of blocks of the input/output circuits in the second direction with the same pitch as that of the input/output circuits.
    Type: Application
    Filed: December 14, 2015
    Publication date: August 4, 2016
    Inventor: Tetsuo ASHIZAWA
  • Patent number: 9087564
    Abstract: An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal operation mode, the bit lines in only memory-cell array blocks to be accessed among the plurality of memory-cell array blocks are precharged in sequence. This allows the peak of precharging current flowing into the SRAM macro to be dispersed.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: July 21, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Tetsuo Ashizawa
  • Publication number: 20150064115
    Abstract: Novel liposomal nanoparticle that has been engineered to be particularly useful for the delivery of compounds to cells found in the peripheral nervous system, and to endothelial cells that form the blood brain barrier. These nanoparticles are intended to be useful for the delivery of compounds suitable for therapeutic purposes and imaging contrast agents that may not otherwise gain access to neuronal axons, or glial cells regions of the brain. Particularly advantageous for the purpose of targeting neural cells, endothelial cells of the blood vessels and epithelial cells of the choroid plexus that serve the brain is the inclusion, in the nanoparticles of cholesterol that surprisingly increases the affinity of the nanoparticles for such as Schwann cells, glial cells, and the like. Image contrast agents, such as those suitable for use in MRI techniques may also be delivered to neural cells, including of the peripheral nervous system.
    Type: Application
    Filed: March 6, 2013
    Publication date: March 5, 2015
    Inventors: Ana M. Ashizawa, Lucia Notterpek, Tetsuo Ashizawa
  • Patent number: 8771965
    Abstract: The present invention concerns the methods and compositions involving nucleic acids with long repeat sequences. In some embodiments of the invention, there are methods for generating such a nucleic acid, and in other methods, there are methods for using such a nucleic acid to screen for candidate therapeutic compounds. Furthermore the present invention relates to methods of screening for Notch inhibitors and other substances that may be used to treat muscle loss and wasting.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: July 8, 2014
    Assignee: The Board of Regents of the University of Texas System
    Inventors: Partha Sarkar, Tetsuo Ashizawa, Weidong Xu
  • Patent number: 8467461
    Abstract: 2n data transfer signal lines are provided between transmitting and receiving sides of data on n signal lines in order to reduce power consumption required for a data transfer even if the number of bits of data to be transferred increases. The transmitting side has an encoder for outputting a signal of a low potential to one signal line and a signal of a high potential to the other signal lines among the 2n data transfer signal lines in response to an input of transfer data from the n signal lines. The receiving side has a decoder for outputting the similar data as the transfer data to n signal lines in response to inputs from the 2n data transfer signal lines.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideyuki Amada, Tetsuo Ashizawa, Hideo Akiyoshi
  • Publication number: 20120287741
    Abstract: An SRAM macro operates in a normal operation mode in which a plurality of memory-cell array blocks are accessible and in a low power mode in which bit lines in the memory-cell array blocks are left floating. When the SRAM macro returns from the low power mode to the normal operation mode, the bit lines in only memory-cell array blocks to be accessed among the plurality of memory-cell array blocks are precharged in sequence. This allows the peak of precharging current flowing into the SRAM macro to be dispersed.
    Type: Application
    Filed: April 11, 2012
    Publication date: November 15, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Tetsuo ASHIZAWA
  • Publication number: 20120171222
    Abstract: The present invention concerns the methods and compositions involving nucleic acids with long repeat sequences. In some embodiments of the invention, there are methods for generating such a nucleic acid, and in other methods, there are methods for using such a nucleic acid to screen for candidate therapeutic compounds. Furthermore the present invention relates to methods of screening for Notch inhibitors and other substances that may be used to treat muscle loss and wasting.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 5, 2012
    Applicant: The Board of Regents of the University of Texas System
    Inventors: Partha Sarkar, Tetsuo Ashizawa, Weidong Xu
  • Patent number: 8027233
    Abstract: An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: September 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tetsuo Ashizawa, Hiromi Honma
  • Publication number: 20110051576
    Abstract: An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced.
    Type: Application
    Filed: June 8, 2010
    Publication date: March 3, 2011
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tetsuo Ashizawa, Hiromi Honma
  • Publication number: 20110033480
    Abstract: The present invention concerns the methods and compositions involving nucleic acids with long repeat sequences. In some embodiments of the invention, there are methods for generating such a nucleic acid, and in other methods, there are methods for using such a nucleic acid to screen for candidate therapeutic compounds. Furthermore the present invention relates to methods of screening for Notch inhibitors and other substances that may be used to treat muscle loss and wasting.
    Type: Application
    Filed: April 11, 2007
    Publication date: February 10, 2011
    Inventors: Partha Sarkar, Tetsuo Ashizawa, Weidong XU
  • Patent number: 7864621
    Abstract: Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A logic of the decoder unit is formed by assigning a bit of the address signal to identify the memory blocks and the couple control units lower than a bit of the address signal to identify the word line groups. Accordingly, the numbers of word lines disposed at the memory blocks can be equalized with each other, and lengths of the bit lines can be shortened. As a result, a wiring delay of each of the bit lines can be minimized, and an access time of a compiled memory can be shortened.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: January 4, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tetsuo Ashizawa
  • Publication number: 20100002778
    Abstract: 2n data transfer signal lines are provided between transmitting and receiving sides of data on n signal lines in order to reduce power consumption required for a data transfer even if the number of bits of data to be transferred increases. The transmitting side has an encoder for outputting a signal of a low potential to one signal line and a signal of a high potential to the other signal lines among the 2n data transfer signal lines in response to an input of transfer data from the n signal lines. The receiving side has a decoder for outputting the similar data as the transfer data to n signal lines in response to inputs from the 2n data transfer signal lines.
    Type: Application
    Filed: September 11, 2009
    Publication date: January 7, 2010
    Applicant: Fujitsu Microelectronics Limited
    Inventors: Hideyuki Amada, Tetsuo Ashizawa, Hideo Akiyoshi
  • Publication number: 20090244988
    Abstract: Each of memory blocks includes word line groups each having at least one of word lines, memory cells and bit lines. A decoder unit selects couple control units corresponding to the memory blocks to be accessed, and decodes an address signal to select any of the word line groups. A logic of the decoder unit is formed by assigning a bit of the address signal to identify the memory blocks and the couple control units lower than a bit of the address signal to identify the word line groups. Accordingly, the numbers of word lines disposed at the memory blocks can be equalized with each other, and lengths of the bit lines can be shortened. As a result, a wiring delay of each of the bit lines can be minimized, and an access time of a compiled memory can be shortened.
    Type: Application
    Filed: June 11, 2009
    Publication date: October 1, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Tetsuo Ashizawa
  • Patent number: 7292493
    Abstract: An electric fuse is formed over a semiconductor substrate, the electric fuse being broken when a current flows therethrough. A breaker transistor is formed in a first surface layer of the semiconductor substrate of a first conductivity type, the breaker transistor including a source region, a drain region and a gate electrode. The source and drain regions sandwiches a channel region. The gate electrode controls a conduction state between the source and drain regions. The drain region is connected to one end of the electric fuse. A breaker pad is connected to the end of the electric fuse to supply a fusing current to the electric fuse. A back-bias pad applies a fixed voltage to the first surface layer independently from both a power supply voltage and a ground potential. A fuse information read circuit reads a breakdown/non-breakdown state of the electric fuse.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: November 6, 2007
    Assignee: Fujitsu Limited
    Inventor: Tetsuo Ashizawa
  • Publication number: 20070230079
    Abstract: A semiconductor device includes: an electrical fuse whose one end is connected to a power source via a switch; an electrical fuse whose one end is connected to ground via a switch; a switch that is connected between the other ends of the electrical fuses and the ground and is selected when the electrical fuses are to be cut; and a first pad and a second pad connected to the one-side ends of the electrical fuses respectively. Cutting electric current is supplied from the first or second pad according to information to be recorded, thereby cutting one of the electrical fuses, so that one-bit information is recorded by the two electrical fuses. This eliminates a need for a latch circuit that holds cut information on the fuses and enables recording and outputting of accurate fuse cut information.
    Type: Application
    Filed: July 27, 2006
    Publication date: October 4, 2007
    Inventor: Tetsuo Ashizawa
  • Publication number: 20070171691
    Abstract: An electric fuse is formed over a semiconductor substrate, the electric fuse being broken when a current flows therethrough. A breaker transistor is formed in a first surface layer of the semiconductor substrate of a first conductivity type, the breaker transistor including a source region, a drain region and a gate electrode. The source and drain regions sandwiches a channel region. The gate electrode controls a conduction state between the source and drain regions. The drain region is connected to one end of the electric fuse. A breaker pad is connected to the end of the electric fuse to supply a fusing current to the electric fuse. A back-bias pad applies a fixed voltage to the first surface layer independently from both a power supply voltage and a ground potential. A fuse information read circuit reads a breakdown/non-breakdown state of the electric fuse.
    Type: Application
    Filed: July 31, 2006
    Publication date: July 26, 2007
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuo Ashizawa
  • Patent number: 6990034
    Abstract: A plurality of p-MOSFETs connected to a power supply line is turned on to precharge bit lines. A precharge cancel signal generated by a NOR circuit and an inverter performs precharge control to turn off the p-MOSFETs to set the bit lines in a floating state during the period of a standby mode, or turn on the p-MOSFETs to precharge the bit lines during the period of a read mode or write mode.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: January 24, 2006
    Assignee: Fujitsu Limited
    Inventor: Tetsuo Ashizawa
  • Patent number: 6963511
    Abstract: A shift register is sequentially supplied via a clock pad and a data pad with a clock and data indicating whether or not an electric fuse circuit is cut off. The supply turns on a switch corresponding to an electric fuse circuit to cut off, and connects the electric fuse circuits to cut off to a voltage supply line. Here, by supplying a high voltage to the voltage supply line via a voltage pad, electric current flows through electric fuse circuits to cut off in each chip area, thereby cutting off the electric fuse circuits at the same time. Providing the clock pad, data pad, voltage pad common to the electric fuse circuits in each chip area makes it possible to reduce the size of a scribe area. This allows increase in the number of semiconductor chips producible per semiconductor wafer, resulting in reduced manufacturing cost thereof.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: November 8, 2005
    Assignee: Fujitsu Limited
    Inventor: Tetsuo Ashizawa
  • Publication number: 20050201165
    Abstract: A shift register is sequentially supplied via a clock pad and a data pad with a clock and data indicating whether or not an electric fuse circuit is cut off. The supply turns on a switch corresponding to an electric fuse circuit to cut off, and connects the electric fuse circuits to cut off to a voltage supply line. Here, by supplying a high voltage to the voltage supply line via a voltage pad, electric current flows through electric fuse circuits to cut off in each chip area, thereby cutting off the electric fuse circuits at the same time. Providing the clock pad, data pad, voltage pad common to the electric fuse circuits in each chip area makes it possible to reduce the size of a scribe area. This allows increase in the number of semiconductor chips producible per semiconductor wafer, resulting in reduced manufacturing cost thereof.
    Type: Application
    Filed: July 28, 2004
    Publication date: September 15, 2005
    Inventor: Tetsuo Ashizawa