Patents by Inventor Tetsuo Ashizawa

Tetsuo Ashizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6917538
    Abstract: A word line control circuit controls a high-level voltage value representing that a plurality of word lines are unselected in each of an access mode and non-access mode on the basis of a control signal for controlling the high-level voltage value of the word lines and a control signal output from a main decoder.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: July 12, 2005
    Assignee: Fujitsu Limited
    Inventor: Tetsuo Ashizawa
  • Patent number: 6914797
    Abstract: First buffers of a first driver circuit generate voltages to be supplied to word lines, respectively. Second buffers of a second driver circuit operate in synchronization with the first buffers to generate voltages to be supplied to first substrate lines, respectively. Each second buffer, upon access to memory cells, supplies a voltage for lowering the threshold values of transfer transistors and driver transistors to its corresponding first substrate line, and supplies thereto a voltage for raising the threshold values of the transfer transistors and the driver transistors during standby. This can improve the operation speed at the time of accessing the memory cells and reduce the leak current during standby. This results in shortening the access time during the operation of the semiconductor memory and reducing the standby current during standby.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: July 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki
  • Patent number: 6876587
    Abstract: A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: April 5, 2005
    Assignee: Fujitsu Limited
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki
  • Patent number: 6855497
    Abstract: Included is a method for detecting spinocerebellar ataxia type 10 (SCA10) by measuring the presence or absence of a DNA expansion in a gene locus associated with spinocerebellar ataxia type 10. The method employs extracting DNA from a sample to be tested, amplifying the extracted DNA; and identifying the presence or absence of a DNA expansion in the amplified extension products. Also included in the present invention are a kit for diagnosis of SCA10 and non-human transgenic eukaryotes that are not expressing or overexpressing SCA10.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: February 15, 2005
    Assignee: Baylor College of Medicine
    Inventors: Tetsuo Ashizawa, Tohru Matsuura
  • Publication number: 20040190323
    Abstract: A semiconductor memory device comprises a memory cell array, a decoder unit selecting a word line of the memory cell array, a first dummy cell array connected to a first dummy bit line and disposed with the memory cell array at a first location away from the decoder unit along the word line, a second dummy cell array connected to second dummy bit lines and disposed with the memory cell array at a second location away from the decoder unit along the word line, the second location being farther from the decoder unit than the first location, and a timing control unit determining timing of activation and deactivation of an internal control signal.
    Type: Application
    Filed: October 28, 2003
    Publication date: September 30, 2004
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki
  • Publication number: 20040042326
    Abstract: A word line control circuit controls a high-level voltage value representing that a plurality of word lines are unselected in each of an access mode and non-access mode on the basis of a control signal for controlling the high-level voltage value of the word lines and a control signal output from a main decoder.
    Type: Application
    Filed: August 12, 2003
    Publication date: March 4, 2004
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuo Ashizawa
  • Publication number: 20040042325
    Abstract: A plurality of p-MOSFETs connected to a power supply line is turned on to precharge bit lines. A precharge cancel signal generated by a NOR circuit and an inverter performs precharge control to turn off the p-MOSFETs to set the bit lines in a floating state during the period of a standby mode, or turn on the p-MOSFETs to precharge the bit lines during the period of a read mode or write mode.
    Type: Application
    Filed: August 8, 2003
    Publication date: March 4, 2004
    Applicant: Fujitsu Limited
    Inventor: Tetsuo Ashizawa
  • Publication number: 20040032768
    Abstract: First buffers of a first driver circuit generate voltages to be supplied to word lines, respectively. Second buffers of a second driver circuit operate in synchronization with the first buffers to generate voltages to be supplied to first substrate lines, respectively. Each second buffer, upon access to memory cells, supplies a voltage for lowering the threshold values of transfer transistors and driver transistors to its corresponding first substrate line, and supplies thereto a voltage for raising the threshold values of the transfer transistors and the driver transistors during standby. This can improve the operation speed at the time of accessing the memory cells and reduce the leak current during standby. This results in shortening the access time during the operation of the semiconductor memory and reducing the standby current during standby.
    Type: Application
    Filed: July 30, 2003
    Publication date: February 19, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuo Ashizawa, Wataru Yokozeki
  • Publication number: 20020146713
    Abstract: Included is a method for detecting spinocerebellar ataxia type 10 (SCA10) by measuring the presence or absence of a DNA expansion in a gene locus associated with spinocerebellar ataxia type 10. The method employs extracting DNA from a sample to be tested, amplifying the extracted DNA; and identifying the presence or absence of a DNA expansion in the amplified extension products. Also included in the present invention are a kit for diagnosis of SCA10 and non-human transgenic eukaryotes that are not expressing or overexpressing SCA10.
    Type: Application
    Filed: August 29, 2001
    Publication date: October 10, 2002
    Inventors: Tetsuo Ashizawa, Tohru Matsuura
  • Patent number: 6339627
    Abstract: A synchronization detector has three registers to memorize individual patterns of three successive frames. A decoder produces a frame location signal on the basis of the individual patterns. A pointer circuit counts the number of the frame location signal to produce a pointer signal. The decoder produces a count-up signal when it can decode the individual patterns. The decoder produces a reset signal when it can not decode the individual patterns. A counter counts the count-up signal and is reset by the reset signal. A register holds a predetermined value. A comparator compares the count value of the counter with the predetermined value. The comparator produces a comparing order signal when the predetermined value is less than the count value. A comparing circuit compares the frame location signal with the pointer signal. If the frame location signal is not equal to the pointer signal, it happens that an optical head skips a few frames or slips to a next truck.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: January 15, 2002
    Assignee: NEC Corporation
    Inventor: Tetsuo Ashizawa
  • Patent number: 6048529
    Abstract: The invention relates to a procedure for synthesis of well-defined conjugates of peptides to the tolerogenic polymer monomethoxypolyethylene glycol (mPEG) or polyvinyl alcohol (PVA). This method results in the preparation of conjugates in which one molecule of tolerogenic polymer is specifically coupled to one or the other or both of the termini of an otherwise unaltered peptide molecule. A synthetic peptide synthesized using this method and corresponding to a myasthenogenic region of an acetylcholine receptor was conjugated to monomethoxypolyethylene glycol. Injection of animals with the mPEG-conjugate and subsequent immunization with whole receptor suppressed the development of experimental autoimmune myasthenia gravis (EAMG) by electrophysiological criteria. Specifically-conjugated, tolerogenic peptides are also disclosed for diseases as diverse as ragweed pollen allergy and Grave's disease.
    Type: Grant
    Filed: March 29, 1995
    Date of Patent: April 11, 2000
    Inventors: M. Zouhair Atassi, Tetsuo Ashizawa
  • Patent number: 5578496
    Abstract: This invention is directed towards peptidic compositions, methods, and diagnostic kits for the accurate and sensitive detection of human acetylcholine receptor (AChR) autoantibodies associated with the disease myasthenia gravis (MG). Eighteen synthetic overlapping oligopeptides encompassing the entire extracellular domain (residues .alpha.1-210) of the .alpha.-chain of human AChR and an additional peptide (residues .alpha.262-276) corresponding to the extracellular connection between the two transmembrane regions were prepared. The immunologic reactivity of these peptides against autoantibodies in the plasma of patients with MG was ascertained by solid-phase radioimmunoassay. Autoantibody responses were subjected to genetic regulation as indicated by the variation in recognition profiles from patient to patient. However, it was possible to detect AChR autoantibodies in a heterogenous patient population by employing a peptide mixture comprising at least four peptides (SEQ ID NOS. 8, 17, 18, and 23).
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: November 26, 1996
    Assignee: Board of Regents, Baylor College of Medicine
    Inventors: M. Zouhair Atassi, Tetsuo Ashizawa