Abstract: A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: Parasitic capacitance in a through-silicon via (TSV) is reduced. A semiconductor apparatus includes a given layer. A via vertically penetrates the given layer. A conductor is in contact with an upper surface side material and a lower surface side material of the vertically penetrated layer. The conductor forms, between the conductor and an inside of the via, a cavity portion that vertically penetrates the layer without being in contact with the inside of the via. At least either the upper surface side material or the lower surface side material of the layer is a conductive material, and at least part of the conductive material includes an opening portion for the cavity portion. This opening portion is used to supply an etchant during etching.

Abstract: A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: A semiconductor device includes a base, a first FET that includes at least two laminated channel structure portions, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: A solid-state image sensor according to the present disclosure includes a first semiconductor substrate having a photoelectric conversion element and a second semiconductor substrate facing the first semiconductor substrate with an insulating film interposed therebetween, in which the second semiconductor substrate has an amplification transistor that amplifies an electrical signal output from the photoelectric conversion element on a first main surface (MSa), has a region having a resistance lower than a resistance of the second semiconductor substrate on a second main surface (MSb) opposite to the first main surface (MSa), and is grounded via the region.

Abstract: A semiconductor device includes a base, a first FET 10n that includes at least two channel structure portions 11n laminated, the channel structure portions 11n each including a channel portion 13n having a nanowire structure 12n, a gate insulation film, and a gate electrode 27n, and a second FET 20n that includes a channel forming layer 23n, a gate insulation layer, and a gate electrode 27n. The first FET 10n and the second FET 20n are provided above the base. The channel portions 13n of the first FET 10n are disposed apart from each other in a laminating direction of the channel structure portions 11n. Assuming that each of a distance between the channel portions 13n of the first FET 10n is a distance L1 and that a thickness of the gate insulation layer of the second FET 20n is a thickness T2, T2?(L1/2) is satisfied.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: an SOI substrate in which a silicon substrate layer, a first insulating layer, and a semiconductor layer are layered in this order; a first transistor provided on the semiconductor layer; a second transistor provided on the silicon substrate layer and withstanding a higher voltage than the first transistor; and an element separation film provided between the first transistor and the second transistor, in which the element separation film includes a second insulating layer embedded in an opening that penetrates the semiconductor layer and the first insulating layer and reaches an inside of the silicon substrate layer, and a portion of the second insulating layer constitutes a gate insulating film of the second transistor.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: an SOI substrate in which a silicon substrate layer, a first insulating layer, and a semiconductor layer are layered in this order; a first transistor provided on the semiconductor layer; a second transistor provided on the silicon substrate layer and withstanding a higher voltage than the first transistor; and an element separation film provided between the first transistor and the second transistor, in which the element separation film includes a second insulating layer embedded in an opening that penetrates the semiconductor layer and the first insulating layer and reaches an inside of the silicon substrate layer, and a portion of the second insulating layer constitutes a gate insulating film of the second transistor.

Abstract: The manufacturing method uses a substrate body comprising a semiconductor substrate having a cell region (1) for forming a memory cell portion and a circuit region (2) for forming a peripheral circuit portion, in which a diffusion layer is formed to the semiconductor substrate in the circuit region (2) and a first interlayer insulation film is formed on the semiconductor substrate, and comprises conducting a step of forming a peripheral circuit including a step of forming a connection hole through a first interlayer insulation film in the circuit region (2) so as to expose the diffusion layer at the bottom, a step of ion implanting impurities to the diffusion layer in the vicinity of the bottom of the connection hole and a step of conducting a heat treatment for activating the impurities introduced into the diffusion layer. Subsequently, a cell region processing step having a step of forming a capacitor on the substrate body in the cell region (1) is conducted.

Abstract: In a method of fabricating electronic components of the type wherein trenches formed in a substrate are filled up with a filling material deposited by a deposition process achieving etching and deposition concurrently, the improvement which comprises portions of the filling material deposited on those portion of the substrate other than those corresponding to the trenches are leveled up to the same height by an additional deposition of the filling material, or alternatively by a full-surface etch back process. With this leveling of the deposited material, a subsequent polishing operation can be performed smoothly with high accuracy. During the polishing operation, the resistance between a conductive polish-stop layer on the substrate and a surface of a polishing member contacting the substrate is monitored to determine a polish end.

Abstract: A method of forming a multi-layer interconnection in which through-holes are formed in an interlayer insulating layer positioned between two neighboring mid interconnection layers, which through-hole is used for establishing an electrical interconnection between upper and lower interconnection layers, comprising the steps of forming an offset insulating film on said mid interconnection layer such that the patterns of the mid interconnection layer and the offset insulating film are the same; forming a sidewall insulating film on the lateral wall surface of a pattern made up of said mid interconnection layer and the offset insulating film; substantially conformally forming an etch stop layer covering the entire surface of the substrate, said etching stop layer being slower in etch rate than said interlayer insulating film; anisotropically etching said interlayer insulating film in a region having an opening size smaller than the spacing between the interconnecting layers; selectively removing the etching stop l

Abstract: A method of determining an optimum condition of an anti-reflective layer upon forming a resist pattern by exposure with a monochromatic light, forms the anti-reflective layer with these conditions and forms a resist pattern using a novel anti-reflective layer.

Abstract: A method of determining an optimum condition of an anti-reflective layer upon forming a resist pattern by exposure with a monochromatic light, forms the anti-reflective layer with these conditions and forms a resist pattern using a novel anti-reflective layer.

Abstract: A method of determining an optimum condition of an anti-reflective layer upon forming a resist pattern by exposure with a monochromatic light, forms the anti-reflective layer with these conditions and forms a resist pattern using a novel anti-reflective layer.

Abstract: A multilayer resist pattern forming method patterns a lower resist layer formed over the stepped surface of a workpiece by a high-speed, highly anisotropic ion mode etching using an intermediate pattern formed by etching an intermediate layer formed by a high-density plasma CVD process as a substantial etching mask. The intermediate layer formed by the high-density plasma CVD process has a dense film quality and highly resistant to ion bombardment. Therefore, the intermediate resist pattern is neither thinned nor contracted and, consequently, the lower resist pattern can be formed precisely in conformity with the design rule. Since the high-density plasma promotes interaction between source gases to enable the intermediate layer to be formed at a comparatively low processing temperature, which prevents damaging the lower resist layer by heat.

Abstract: A semiconductor device in which patterning is effected using a silicon oxynitride (SiON) based thin film as an anti-reflection film and in which electrical properties are prohibited from being deteriorated by hydrogen contained in the SiON based thin film. The semiconductor device has a substrate, a gate insulating film formed on the surface of the substrate, a gate electrode formed on the gate insulating film, and a first antireflection film having a pattern in common with the gate electrode. The semiconductor device also has a hydrogen permeation prohibiting film formed between the gate insulating film and the first antireflection film. The first antireflection film contains hydrogen and is formed on the gate electrode.

Abstract: A method of forming a metal plug, including a step of flattening by polishing the surface of a contact plug which is formed by etching back a metal layer, for example, a deposited layer of Blk-W on a substrate. It also makes it possible to print a wiring metal layer by a lithographic process which has thus far been considered difficult to apply to Blk-W. In the method of the invention, a contact hole 3 is opened in an insulation film layer 2 on a substrate 1, and, after coating an adhesion layer 4, a metal layer 5 is deposited on the entire surface. Thereafter, the surface of the metal layer 5 is flattened by a polishing operation, and etched back to form a metal plug 7.

Abstract: A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.

Abstract: A method of determining an optimum condition of an anti-reflective layer upon forming a resist pattern by exposure with a monochromatic light, forms the anti-reflective layer with these conditions and forms a resist pattern using a novel anti-reflective layer.

Abstract: A method of forming trench isolation including a burying step of burying trenches by a deposition means for conducting etching and deposition simultaneously and a polishing step of flattening a burying material by polishing is conducted by disposing an isotropic etching step, a multi-layered etching stopper and a protrusion unifying structure. Polishing can be attained with satisfactory flatness uniformly or with no polishing residue even in a portion to be polished in which the etching stopper layer is distributed unevenly. The method can be applied to manufacture of a semiconductor device or the like.