Patents by Inventor Tetsuro ISHIGURO

Tetsuro ISHIGURO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160190278
    Abstract: A compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; and a GaN cap layer formed over the electron supply layer, wherein the electron supply layer includes a first layer made of i-type AlxGa1-xN (0<x<1) and a second layer made of i-type AlyGa1-yN (x<y?1) and formed over the first layer.
    Type: Application
    Filed: November 19, 2015
    Publication date: June 30, 2016
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi Yamada, Tetsuro Ishiguro
  • Patent number: 9312341
    Abstract: A compound semiconductor device includes: a substrate; and a compound semiconductor lamination structure formed over the substrate, the compound semiconductor lamination structure including a buffer layer containing an impurity, and an active layer formed over the buffer layer.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: April 12, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Norikazu Nakamura
  • Patent number: 9269799
    Abstract: A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 23, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Patent number: 9184241
    Abstract: A semiconductor apparatus includes a buffer layer formed on a substrate; an SLS (Strained Layer Supperlattice) buffer layer formed on the buffer layer; an electron transit layer formed on the SLS buffer layer and formed of a semiconductor material; and an electron supply layer formed on the electron transit layer and formed of a semiconductor material. Further, the buffer layer is formed of AlGaN and includes two or more layers with different Al composition ratios, the SLS buffer layer is formed by alternately laminating a first lattice layer including AlN and a second lattice layer including GaN, and the Al composition ratio in one of the layers of the buffer layer being in contact with the SLS buffer layer is greater than or equal to an Al effective composition ratio in the SLS buffer layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: November 10, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Patent number: 9029868
    Abstract: A semiconductor apparatus includes a substrate; a buffer layer formed on the substrate; a first semiconductor layer formed on the buffer layer; and a second semiconductor layer formed on the first semiconductor layer. Further, the buffer layer is formed of AlGaN and doped with Fe, the buffer layer includes a plurality of layers having different Al component ratios from each other, and the Al component ratio of a first layer is greater than the Al component ratio of a second layer and a Fe concentration of the first layer is less than the Fe concentration of the second layer, the first and second layers being included in the plurality of layers, and the first layer being formed on a substrate side of the second layer.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: May 12, 2015
    Assignee: Fujitsu Limited
    Inventors: Junji Kotani, Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Publication number: 20150076509
    Abstract: A semiconductor device includes a buffer layer made of nitride semiconductor on a substrate, a first semiconductor layer made of nitride semiconductor on the buffer layer, a second semiconductor layer made of nitride semiconductor on the first semiconductor layer, and a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer, wherein the buffer layer has elements doped therein that include both an element selected from a group consisting of C, Mg, Fe, and Co and an element selected from a group consisting of Si, Ge, Sn, and O.
    Type: Application
    Filed: August 8, 2014
    Publication date: March 19, 2015
    Inventors: TETSURO ISHIGURO, JUNJI KOTANI, NORIKAZU NAKAMURA
  • Publication number: 20150034967
    Abstract: A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with as impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.
    Type: Application
    Filed: October 16, 2014
    Publication date: February 5, 2015
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuro Ishiguro
  • Patent number: 8878248
    Abstract: A semiconductor device includes a first semiconductor layer formed on a substrate, the first semiconductor containing an impurity element; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; and a gate electrode, a source electrode and a drain electrode that are formed on the third semiconductor layer. In the semiconductor device, the second semiconductor layer includes an impurity diffusion region in which an impurity element contained in the first semiconductor layer is diffused, the impurity diffusion region being located directly beneath the gate electrode and being in contact with the first semiconductor layer, and the impurity element causes the impurity diffusion region to be a p-type impurity diffusion region.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: November 4, 2014
    Assignee: Transphorm Japan, Inc.
    Inventors: Tetsuro Ishiguro, Atsushi Yamada
  • Publication number: 20140291725
    Abstract: A compound semiconductor device includes: a substrate; and a compound semiconductor lamination structure formed over the substrate, the compound semiconductor lamination structure including a buffer layer containing an impurity, and an active layer formed over the buffer layer.
    Type: Application
    Filed: February 21, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, NORIKAZU NAKAMURA
  • Publication number: 20140091318
    Abstract: A semiconductor apparatus includes: a substrate; a buffer layer formed on the substrate; a strained layer superlattice buffer layer formed on the buffer layer; an electron transit layer formed of a semiconductor material on the strained layer superlattice buffer layer; and an electron supply layer formed of a semiconductor material on the electron transit layer; the strained layer superlattice buffer layer being an alternate stack of first lattice layers including AlN and second lattice layers including GaN; the strained layer superlattice buffer layer being doped with one, or two or more impurities selected from Fe, Mg and C.
    Type: Application
    Filed: July 29, 2013
    Publication date: April 3, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura
  • Publication number: 20140091314
    Abstract: A semiconductor apparatus includes a buffer layer formed on a substrate; an SLS (Strained Layer Supperlattice) buffer layer formed on the buffer layer; an electron transit layer formed on the SLS buffer layer and formed of a semiconductor material; and an electron supply layer formed on the electron transit layer and formed of a semiconductor material. Further, the buffer layer is formed of AlGaN and includes two or more layers with different Al composition ratios, the SLS buffer layer is formed by alternately laminating a first lattice layer including AlN and a second lattice layer including GaN, and the Al composition ratio in one of the layers of the buffer layer being in contact with the SLS buffer layer is greater than or equal to an Al effective composition ratio in the SLS buffer layer.
    Type: Application
    Filed: July 5, 2013
    Publication date: April 3, 2014
    Inventors: Tetsuro ISHIGURO, Atsushi YAMADA, Norikazu NAKAMURA
  • Publication number: 20140091313
    Abstract: A semiconductor apparatus includes a substrate; a buffer layer formed on the substrate; a first semiconductor layer formed on the buffer layer; and a second semiconductor layer formed on the first semiconductor layer. Further, the buffer layer is formed of AlGaN and doped with Fe, the buffer layer includes a plurality of layers having different Al component ratios from each other, and the Al component ratio of a first layer is greater than the Al component ratio of a second layer and a Fe concentration of the first layer is less than the Fe concentration of the second layer, the first and second layers being included in the plurality of layers, and the first layer being formed on a substrate side of the second layer.
    Type: Application
    Filed: July 5, 2013
    Publication date: April 3, 2014
    Inventors: Junji KOTANI, Tetsuro ISHIGURO, Atsushi YAMADA, Norikazu NAKAMURA
  • Publication number: 20140091364
    Abstract: An AlGaN/GaN HEMT includes: an electron transit layer; an electron supply layer formed above the electron transit layer; and a gate electrode formed above the electron supply layer, wherein a p-type semiconductor region is formed only at a site of the electron transit layer which is contained in a region below the gate electrode.
    Type: Application
    Filed: August 1, 2013
    Publication date: April 3, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kenji IMANISHI, Atsushi YAMADA, Tetsuro ISHIGURO, Toyoo MIYAJIMA
  • Publication number: 20140091320
    Abstract: A semiconductor device includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a third semiconductor layer and a fourth semiconductor layer formed on the second semiconductor layer, a gate electrode formed on the third semiconductor layer, and a source electrode and a drain electrode contacting and formed on the fourth semiconductor layer, wherein the third semiconductor layer is formed of a semiconductor material for attaining p-type on an area just under the gate electrode, and a concentration of silicon in the fourth semiconductor layer is higher than that in the second semiconductor layer.
    Type: Application
    Filed: August 16, 2013
    Publication date: April 3, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: NORIKAZU NAKAMURA, Atsushi Yamada, Tetsuro Ishiguro, JUNJI KOTANI, Kenji Imanishi
  • Patent number: 8592823
    Abstract: A compound semiconductor device includes: a substrate; a GaN compound semiconductor multilayer structure disposed over the substrate; and a stress relief layer which is AlN-based and which is disposed between the substrate and the GaN compound semiconductor multilayer structure, wherein a surface of the stress relief layer that is in contact with the GaN compound semiconductor multilayer structure includes recesses that have a depth of 5 nm or more and that are formed at a number density of 2×1010 cm?2 or more.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: November 26, 2013
    Assignee: Fujitsu Limited
    Inventors: Junji Kotani, Tetsuro Ishiguro, Shuichi Tomabechi
  • Publication number: 20130256682
    Abstract: An embodiment of a method of manufacturing a compound semiconductor device includes: forming an initial layer over a substrate; forming a buffer layer over the initial layer; forming an electron transport layer and an electron supply layer over the buffer layer; and forming a gate electrode, a source electrode and a gate electrode over the electron supply layer. The forming an initial layer includes: forming a first compound semiconductor film with a flow rate ratio being a first value, the flow rate ratio being a ratio of a flow rate of a V-group element source gas to a flow rate of a III-group element source gas; and forming a second compound semiconductor film with the flow rate ratio being a second value different from the first value over the first compound semiconductor film. The method further includes forming an Fe-doped region between the buffer layer and the electron transport layer.
    Type: Application
    Filed: December 11, 2012
    Publication date: October 3, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada, Norikazu Nakamura, Kenji Imanishi
  • Publication number: 20130248872
    Abstract: A semiconductor device includes: a nucleation layer formed over a substrate; a buffer layer formed over the nucleation layer; a first nitride semiconductor layer formed over the buffer layer; and a second nitride semiconductor layer formed over the first nitride semiconductor layer, wherein the ratio of yellow luminescence emission to band edge emission in photoluminescence is 400% or less and the twist value in an X-ray rocking curve is 1,000 arcsec or less.
    Type: Application
    Filed: February 8, 2013
    Publication date: September 26, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Norikazu NAKAMURA, Atsushi YAMADA, Tetsuro ISHIGURO, Toyoo MIYAJIMA, Kenji IMANISHI
  • Patent number: 8476642
    Abstract: A compound semiconductor device includes a substrate; an initial layer formed over the substrate; and a core layer which is formed over the initial layer and contains a Group III-V compound semiconductor. The initial layer is a layer of Group III atoms of the Group III-V compound semiconductor contained in the core layer.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: July 2, 2013
    Assignee: Fujitsu Limited
    Inventors: Tetsuro Ishiguro, Atsushi Yamada
  • Publication number: 20130075786
    Abstract: A semiconductor device including a high resistance layer formed on a substrate, the high resistance layer being formed with a semiconductor material doped with an impurity element that makes the semiconductor material highly resistant; a multilayer intermediate layer formed on the high resistance layer; an electron transit layer formed with a semiconductor material on the multilayer intermediate layer; and an electron supply layer formed with a semiconductor material on the electron transit layer, wherein the multilayer intermediate layer is formed with a multilayer film in which a GaN layer and an AlN layer are alternately laminated.
    Type: Application
    Filed: July 12, 2012
    Publication date: March 28, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Tetsuro ISHIGURO
  • Publication number: 20130075785
    Abstract: A semiconductor device includes a first semiconductor layer formed on a substrate, the first semiconductor containing an impurity element; a second semiconductor layer formed on the first semiconductor layer; a third semiconductor layer formed on the second semiconductor layer; and a gate electrode, a source electrode and a drain electrode that are formed on the third semiconductor layer. In the semiconductor device, the second semiconductor layer includes an impurity diffusion region in which an impurity element contained in the first semiconductor layer is diffused, the impurity diffusion region being located directly beneath the gate electrode and being in contact with the first semiconductor layer, and the impurity element causes the impurity diffusion region to be a p-type impurity diffusion region.
    Type: Application
    Filed: July 9, 2012
    Publication date: March 28, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro Ishiguro, Atsushi Yamada