Patents by Inventor Tetsuya Ishimaru
Tetsuya Ishimaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8324092Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.Type: GrantFiled: January 5, 2010Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Kan Yasui, Digh Hisamoto, Tetsuya Ishimaru, Shin-Ichiro Kimura
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Patent number: 8125012Abstract: Performance of a non-volatile semiconductor storage device which performs electron writing by hot electrons and hole erasure by hot holes is improved. A non-volatile memory cell which performs a writing operation by electrons and an erasure operation by holes has a p-type well region, isolation regions, a source region, and a drain region provided on an Si substrate. A control gate electrode is formed via a gate insulating film between the source region and the drain region. In a left-side side wall of the control gate electrode, a bottom Si oxide film, an electric charge holding film, a top Si oxide film, and a memory gate electrode are formed. The electric charge holding film is formed from an Si nitride film stoichiometrically excessively containing silicon.Type: GrantFiled: December 15, 2006Date of Patent: February 28, 2012Assignee: Renesas Electronics CorporationInventors: Toshiyuki Mine, Kan Yasui, Tetsuya Ishimaru, Yasuhiro Shimamoto
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Publication number: 20120026798Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: ApplicationFiled: October 7, 2011Publication date: February 2, 2012Inventors: Digh HISAMOTO, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Patent number: 8076709Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.Type: GrantFiled: September 1, 2010Date of Patent: December 13, 2011Assignee: Renesas Electronics CorporationInventors: Tetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura
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Patent number: 8064261Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: GrantFiled: May 25, 2010Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Patent number: 8063433Abstract: A memory cell includes an ONO film composed of a stacked film of a silicon nitride film SIN which is a charge trapping portion and oxide films BOTOX and TOPOX positioned under and over the silicon nitride film, a memory gate electrode MG over the ONO film, a source region MS, and a drain region MD, and program or erase is performed by hot carrier injection in the memory cell. In the memory cell, a total concentration of N—H bonds and Si—H bonds contained in the silicon nitride film SIN is made to be 5×1020 cm?3 or less.Type: GrantFiled: April 24, 2008Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Tetsuya Ishimaru, Yasuhiro Shimamoto, Toshiyuki Mine, Yasunobu Aoki, Koichi Toba, Kan Yasui
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Patent number: 8054680Abstract: Memory cells in which an erase and write operation is performed by injecting electrons from a substrate and extracting the electrons into a gate electrode constitute a semiconductor nonvolatile memory device. That is a gate extraction semiconductor nonvolatile memory device. In that device, if an erase bias is applied in a first process of an erase and write operation, memory cells in an overerase condition occur and the charge retention characteristics of such memory cells are degraded. The present invention provides a semiconductor nonvolatile memory device using means for writing all the memory cells in an erase unit before applying the erase bias, and then applying the erase bias.Type: GrantFiled: May 25, 2004Date of Patent: November 8, 2011Assignee: Renesas Electronics CorporationInventors: Nozomu Matsuzaki, Tetsuya Ishimaru, Makoto Mizuno, Takashi Hashimoto
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Publication number: 20110235419Abstract: In a split gate MONOS memory which carries out rewrite by hot carrier injection, retention characteristics are improved. A select gate electrode of a memory cell is connected to a select gate line, and a memory gate electrode is connected to a memory gate line. A drain region is connected to a bit line, and a source region is connected to a source line. Furthermore, a well line is connected to a p type well region in which the memory cell is formed. When write to the memory cell is to be carried out, write by a source side injection method is carried out while applying a negative voltage to the p type well region via the well line.Type: ApplicationFiled: March 28, 2011Publication date: September 29, 2011Inventors: Tetsuya ISHIMARU, Yasuhiro Shimamoto, Hideo Kasai, Yutaka Okuyama, Tsuyoshi Arigane
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Patent number: 7935597Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: GrantFiled: October 26, 2010Date of Patent: May 3, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Patent number: 7915666Abstract: An erase method where a corner portion on which an electric field concentrates locally is provided on the memory gate electrode, and charges in the memory gate electrode are injected into a charge trap film in a gate dielectric with Fowler-Nordheim tunneling operation is used. Since current consumption at the time of erase can be reduced by the Fowler-Nordheim tunneling, a power supply circuit area of a memory module can be reduced. Since write disturb resistance can be improved, a memory array area can be reduced by adopting a simpler memory array configuration. Owing to both the effects, an area of the memory module can be largely reduced, so that manufacturing cost can be reduced. Further, since charge injection centers of write and erase coincide with each other, so that (program and erase) endurance is improved.Type: GrantFiled: May 20, 2008Date of Patent: March 29, 2011Assignee: Renesas Electronics CorporationInventors: Kan Yasui, Tetsuya Ishimaru, Digh Hisamoto, Yasuhiro Shimamoto
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Publication number: 20110039385Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: ApplicationFiled: October 26, 2010Publication date: February 17, 2011Inventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Patent number: 7872298Abstract: Performance and reliability of a semiconductor device including a non-volatile memory are improved. A memory cell of the non-volatile memory includes, over an upper portion of a semiconductor substrate, a select gate electrode formed via a first dielectric film and a memory gate electrode formed via a second dielectric film formed of an ONO multilayered film having a charge storing function. The first dielectric film functions as a gate dielectric film, and includes a third dielectric film made of silicon oxide or silicon oxynitride and a metal-element-containing layer made of a metal oxide or a metal silicate formed between the select gate electrode and the third dielectric film. A semiconductor region positioned under the memory gate electrode and the second dielectric film has a charge density of impurities lower than that of a semiconductor region positioned under the select gate electrode and the first dielectric film.Type: GrantFiled: July 13, 2007Date of Patent: January 18, 2011Assignee: Renesas Electronics CorporationInventors: Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru, Shinichiro Kimura
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Patent number: 7863131Abstract: Semiconductor device and manufacturing method for reducing the number of required lithography masks added to the nonvolatile memory in the standard CMOS process to shorten the production period and reduce costs. In a split-gate memory cell with silicided gate electrodes utilizing a sidewall structure, a separate auxiliary pattern is formed adjoining the selected gate electrodes. A contact is set on a wiring layer self-aligned by filling side-wall gates of polysilicon in the gap between the electrodes and auxiliary pattern. The contact may overlap onto the auxiliary pattern and device isolation region, in an optimal design considering the size of the occupied surface area. If the distance to the selected gate electrode is x, the ONO film deposit thickness is t, and the polysilicon film deposit thickness is d, then the auxiliary pattern may be separated just by a distance x such that x<2×(t+d).Type: GrantFiled: July 26, 2005Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Kan Yasui, Digh Hisamoto, Tetsuya Ishimaru
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Publication number: 20100322013Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.Type: ApplicationFiled: September 1, 2010Publication date: December 23, 2010Inventors: Tetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura
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Patent number: 7847343Abstract: Provided is a nonvolatile semiconductor memory device having a split gate structure, wherein a memory gate is formed over a convex shaped substrate and side surfaces of it is used as a channel. The nonvolatile semiconductor memory device according to the present invention is excellent in read current driving power even if a memory cell is scaled down.Type: GrantFiled: February 10, 2009Date of Patent: December 7, 2010Assignee: Renesas Electronics CorporationInventors: Digh Hisamoto, Kan Yasui, Shinichiro Kimura, Tetsuya Ishimaru
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Patent number: 7847331Abstract: In a situation where a memory cell includes an ONO film, which comprises a silicon nitride film for charge storage and oxide films positioned above and below the silicon nitride film; a memory gate above the ONO film; a select gate, which is adjacent to a lateral surface of the memory gate via the ONO film; a gate insulator positioned below the select gate; a source region; and a drain region, an erase operation is performed by injecting holes generated by BTBT into the silicon nitride film while applying a positive potential to the source region, applying a negative potential to the memory gate, applying a positive potential to the select gate, and flowing a current from the drain region to the source region, thus improving the characteristics of a nonvolatile semiconductor memory device.Type: GrantFiled: January 10, 2005Date of Patent: December 7, 2010Assignee: Renesas Electronics CorportionInventors: Tetsuya Ishimaru, Digh Hisamoto, Kan Yasui, Shinichiro Kimura
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Publication number: 20100232231Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: ApplicationFiled: May 25, 2010Publication date: September 16, 2010Inventors: Digh HISAMOTO, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Patent number: 7751255Abstract: An operation scheme for operating stably a semiconductor nonvolatile memory device is provided. When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes. Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.Type: GrantFiled: September 19, 2008Date of Patent: July 6, 2010Assignee: Renesas Technology Corp.Inventors: Digh Hisamoto, Kan Yasui, Tetsuya Ishimaru, Shinichiro Kimura, Daisuke Okada
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Patent number: 7709315Abstract: An interface between a bottom oxide film and a silicon nitride film in a neighborhood of a bottom part of a select gate is located at a position as high as or higher than that of an interface between a silicon substrate (p-type well) and a gate insulating film (d?0) Further, the gate insulating film and the bottom oxide film are successively and smoothly jointed in the neighborhood of the bottom part of the select gate. By this configuration, localization in a distribution of electrons injected into the silicon nitride film in the writing is mitigated and electrons to be left unerased by hot-hole erasing are reduced. Therefore, not only the increase ratio of the electrons left unerased in the writing can be reduced, but also the problem in which the threshold voltage does not decrease to the predetermined voltage in the deletion can be suppressed.Type: GrantFiled: July 5, 2007Date of Patent: May 4, 2010Assignee: Renesas Technology Corp.Inventors: Naoki Tega, Hiroshi Miki, Yasuhiro Shimamoto, Digh Hisamoto, Tetsuya Ishimaru
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Publication number: 20100105199Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.Type: ApplicationFiled: January 5, 2010Publication date: April 29, 2010Inventors: Kan Yasui, Digh Hisamoto, Tetsuya Ishimaru, Shin-Ichiro Kimura