Abstract: Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.

Abstract: According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

Abstract: According to one embodiment, a semiconductor device performs processing based on a user program by using a user program, which is used in a normal mode, as an analysis program and making a plurality of peripheral circuits having the same function operate in lock-step where the plurality of peripheral circuits operate in the identical manner, and makes failure diagnosis of the peripheral circuits by determining match or mismatch of a plurality of analysis information respectively obtained from the plurality of peripheral circuits operating in lock-step.

Abstract: Related semiconductor devices have a problem in which analysis processing with high defect reproducibility cannot be performed. According to an embodiment, a semiconductor device includes a first arithmetic core that executes a first program stored in a first code area using a first local memory area and a second arithmetic core that executes a second program stored in a second code area using a second local memory area. In an analysis mode, the semiconductor device performs first analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the first program and second analysis processing that causes both the first arithmetic core and the second arithmetic core to execute the second program, and compares a plurality of arithmetic result data pieces acquired from the first and second analysis processing to thereby acquire analysis information used for defect analysis.

Abstract: A semiconductor device includes a bus, first and second bus drivers that drive the bus, and a control circuit that controls the first and second bus drivers. The control circuit controls the first and second bus drivers in such a way that the first and second bus drivers supply logic signals different from each other to the bus.

Abstract: A method for providing the layout design of semiconductor integrated circuit that is capable of promoting the reduction of the circuit pattern area is provided. A hole pattern is disposed at the mesh point which is an intersecting point of mutually orthogonal virtual grid lines and another hole pattern is not disposed at the adjacent mesh point that is the closed mesh point having the hole pattern thereon.

Abstract: A method for providing the layout design of semiconductor integrated circuit that is capable of promoting the reduction of the circuit pattern area is provided. A hole pattern is disposed at the mesh point which is an intersecting point of mutually orthogonal virtual grid lines and another hole pattern is not disposed at the adjacent mesh point that is the mostly closed mesh point having the hole pattern thereon.

Abstract: In the semiconductor device disclosed in the present invention, the well regions in the internal circuit comprise high-impurity-concentration regions 4 and 5 as lower layers and low-impurity-concentration regions 2 and 3 as upper layers, and the well regions in the I/O-protective circuit comprise only low-impurity-concentration regions 11 and 12. As a result, there can be realized an internal circuit having good latch-up resistance and an I/O-protective circuit having good static surge resistance.

Abstract: A silicon-on-insulator structure in a field effect transistor is formed on an insulation region. A body region of a first conductivity type is selectively formed on an insulation region. A diffusion region of a second conductivity type is selectively formed on the insulation region and in one side of the body region. An isolation layer is selectively formed on the insulation region and is bounded with the diffusion region so that the diffusion region is positioned between the body region and the isolation layer. A body contact region of the first conductivity type is selectively formed on the insulation region and is bounded with the isolation layer so that the body contact region is isolated by the isolation layer from the diffusion region.

Abstract: The present invention provides a fuse structure formed in an inter-layer insulator having a first level interconnection and a second level interconnection isolated by the inter-layer insulator from the first level interconnection. The fuse structure comprises a conductive plug for providing an electrical connection between a first connecting part of the first level interconnection and a second connecting part of the second level interconnection, wherein the fuse structure further comprises at least a void which extends within the inter-layer insulator and also at least a part of the void extends adjacent to the second connecting part of the second level interconnection, so that when the second connecting part is rapidly evaporated by receiving a thermal energy, an evaporated material of the second connecting part is deposited on an inner wall of the void for causing an electrical disconnection between the first and second interconnections.

Abstract: A checking transistor for checking selected regions a semiconductor substrate containing radiation-hardened semiconductor circuitry having a plurality of transistors according to the present invention comprises a source region of the other conductivity type and a drain region of the other conductivity type formed on the semiconductor substrate through the same fabrication steps as those used to fabricate usual transistors, a second impurity region of the one conductivity type formed between the source region and the drain region through the same fabrication steps as those used to fabricate the first impurity region, an oxide film formed on the source region, the drain region and the second impurity region, the oxide film having the same thickness as that of the second field oxide film, an insulating film provided on the oxide film, the insulating film having the same thickness as that of the interlayer insulating film and a gate. electrode provided on the insulating film.

Abstract: Disclosed is a semiconductor device, which has: a first device-separating insulating film which is formed on a semiconductor substrate and extends in a first(Y) direction; a second device-separating insulting film which is formed on said semiconductor substrate and extends in a second(X) direction normal to the first(Y) direction; a first-conductivity-type device region which is formed on the semiconductor substrate and is sectioned by the first and second device-separating insulating films; and a first first-conductive-type high concentration impurity layer which is formed under the first device-separating insulating film and extends in the first(Y) direction; wherein the second device-separating insulating film is connected with the first device-separating insulating film through an insulating film thinner than both the first and second device-separating insulating films, the thin insulating film extending over the first high concentration impurity layer to separate the device region arranged in the second(

Abstract: On a semiconductor substrate (1), there are provided field oxide films (2,3,4), a gate oxide film (5), thin oxide films (6, 6) with film thickness almost equal to that of the gate oxide film (5), and a gate electrode (7). An oxide film (8) of the same thickness as the gate oxide film (5) is also provided so as to separate the field oxide films (3) and (4), to overlap a portion of the gate electrode (7). A high-concentration impurity layer (11, 12) is formed under each of the thin oxide films (6, 8). Source-drain areas (9, 10) are provided with end portions separated from the high-concentration impurity layer (12) and the field oxide films (3, 4).