Patents by Inventor Tetsuya Nakajima

Tetsuya Nakajima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6953273
    Abstract: A vehicle lamp has first and second lamp chamber portions each including: a light source; a casing having opening and portion for reflecting light emitted from the light source; and lens portion for closing the opening of the casing; the first and second lamp chamber portions each forming lamp chamber partitioned with the casing and the lens portion, wherein the lens portion of the first lamp chamber portion passes light through substantially forward or backward from a vehicle; at least a part of the second lamp chamber portion is disposed within the lamp chamber of the first lamp chamber portion; and the second lamp chamber portion overlaps with the light source of the first lamp chamber portion in the substantially longitudinal direction.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: October 11, 2005
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Tetsuya Nakajima, Atsushi Kochi
  • Patent number: 6787412
    Abstract: It is disclosed a dielectric element comprising a lower electrode, a dielectric layer, and an upper electrode which are provided on a substrate, in which at least one of the electrodes is a Pt layer, a Ru layer is used as a base layer for the Pt layer. In the fabrication of the dielectric element, the Pt layer is formed by electroplating, a photoresist pattern is used as a plating mask, and an Ru layer is formed as a seed layer. The present invention makes it possible to provide a dielectric element using Pt as an electrode material, that is capable of easily forming a Pt electrode having excellent electrical characteristics without generating voids or seams, that is capable of forming a fine pattern, and that does not occur contamination in a processing chamber, and a method for fabricating a dielectric element of having the characteristics mentioned above.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: September 7, 2004
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Akira Hashimoto, Yoshimi Sato, Atsushi Kawakami, Hideya Kobari, Tetsuya Nakajima
  • Publication number: 20040008521
    Abstract: A vehicle lamp has first and second lamp chamber portions each including: a light source; a casing having opening and portion for reflecting light emitted from the light source; and lens portion for closing the opening of the casing; the first and second lamp chamber portions each forming lamp chamber partitioned with the casing and the lens portion, wherein the lens portion of the first lamp chamber portion passes light through substantially forward or backward from a vehicle; at least a part of the second lamp chamber portion is disposed within the lamp chamber of the first lamp chamber portion; and the second lamp chamber portion overlaps with the light source of the first lamp chamber portion in the substantially longitudinal direction.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 15, 2004
    Applicant: Fuji Jukogyo Kabushiki Kaisha
    Inventors: Tetsuya Nakajima, Atsushi Kochi
  • Publication number: 20030209747
    Abstract: It is disclosed a dielectric element comprising a lower electrode, a dielectric layer, and an upper electrode which are provided on a substrate, in which at least one of the electrodes is a Pt layer, a Ru layer is used as a base layer for the Pt layer. In the fabrication of the dielectric element, the Pt layer is formed by electroplating, a photoresist pattern is used as a plating mask, and an Ru layer is formed as a seed layer. The present invention makes it possible to provide a dielectric element using Pt as an electrode material, that is capable of easily forming a Pt electrode having excellent electrical characteristics without generating voids or seams, that is capable of forming a fine pattern, and that does not occur contamination in a processing chamber, and a method for fabricating a dielectric element of having the characteristics mentioned above.
    Type: Application
    Filed: June 11, 2003
    Publication date: November 13, 2003
    Inventors: Akira Hashimoto, Yoshimi Sato, Atsushi Kawakami, Hideya Kobari, Tetsuya Nakajima
  • Patent number: 6597027
    Abstract: It is disclosed a dielectric element comprising a lower electrode, a dielectric layer, and an upper electrode which are provided on a substrate, in which at least one of the electrodes is a Pt layer, a Ru layer is used as a base layer for the Pt layer. In the fabrication of the dielectric element, the Pt layer is formed by electroplating, a photoresist pattern is used as a plating mask, and an Ru layer is formed as a seed layer. The present invention makes it possible to provide a dielectric element using Pt as an electrode material, that is capable of easily forming a Pt electrode having excellent electrical characteristics without generating voids or seams, that is capable of forming a fine pattern, and that does not occur contamination in a processing chamber, and a method for fabricating a dielectric element of having the characteristics mentioned above.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: July 22, 2003
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Akira Hashimoto, Yoshimi Sato, Atsushi Kawakami, Hideya Kobari, Tetsuya Nakajima
  • Publication number: 20020098296
    Abstract: There is disclosed a gas barrier film having, as a base film, a polypropylene film, which makes it possible to take advantage of the excellent gas barrier property inherent to an SiOx thin film formed on the polypropylene film, and which is free from chlorine which would give a bad influence to the environment. This gas barrier film comprises a polypropylene film whose surface is bonded with tuning molecular chains having, as a main skeleton, an —O—Si—O— structure by enabling the oxygen (—O—) thereof to be bonded to carbon atoms of the surface of the polypropylene film, and an SiOx thin film formed on the surface of the polypropylene film where the tuning molecular chains are bonded, the SiOx thin film being bonded to the tuning molecular chains interposed between the polypropylene film and the SiOx thin film.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 25, 2002
    Applicant: PRES. OF SHIZUOKA UNIV., A JAPANESE GOV. AGENCY
    Inventors: Norihiro Inagaki, Shigeru Tasaka, Tetsuya Nakajima
  • Patent number: 6353078
    Abstract: The present invention provides an adhesive comprising a polyester polyol or polyurethane polyol possessing structural units represented by the following general formula (I) within its molecular structure, and an organic polyisocyanate in which the isocyanate groups may be protected: wherein R1 and R2 are the same or different and each represents lower alkyl. The adhesive of the present invention exhibits an excellent initial adhesion strength; and provides adhered objects that exhibit an excellent permanent adhesion strength, hot water resistance, flexibility, flexibility at a low temperature, and fatigue resistance, and is useful in adhering plastic, metal, and the like. In addition, the present invention provides a method of mixing the aforementioned components and using the mixture for adhesion, and a use of the mixture of the aforementioned components.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: March 5, 2002
    Assignee: Kyowa Yuka Co., Ltd.
    Inventors: Shigeru Murata, Masahiko Yasuda, Tetsuya Nakajima
  • Patent number: 6120969
    Abstract: Disclosed is, for example, bis(2,5-dimethyl-3-(2-hydroxy-5-ethylbenzyl)-4-hydroxyphenyl)methane and quinonediazide ester thereof. These are used for positive photoresist compositions. According to the invention, positive photoresist compositions having a high definition, a high sensitivity and a large exposure margin can be provided.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: September 19, 2000
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Mitsuo Hagihara, Kousuke Doi, Hidekatsu Kohara, Toshimasa Nakayama, Tetsuya Nakajima
  • Patent number: 6087466
    Abstract: The present invention provides a polyester polyol comprising within its molecular structure both structural units respectively represented by the following general formula (I) and general formula (II). In addition, the present invention provides a polyurethane using the polyester polyol of the present invention. This polyurethane exhibits excellent resistance to hydrolysis, resistance to alkali, mechanical strength, and the like. ##STR1## (wherein R.sup.1 and R.sup.2 are the same or different and each represents lower alkyl having 1 to 8 carbon atoms), ##STR2## (wherein R.sup.3 and R.sup.4 are the same or different and each represents lower alkyl having 1 to 8 carbon atoms).
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: July 11, 2000
    Assignee: Kyowa Yuka Co., Ltd.
    Inventors: Shigeru Murata, Yukio Inaba, Masahiko Yasuda, Tetsuya Nakajima
  • Patent number: 5672895
    Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.
    Type: Grant
    Filed: December 19, 1995
    Date of Patent: September 30, 1997
    Assignee: Fujitsu, Ltd.
    Inventors: Takashi Iida, Satoru Sumi, Hiroshi Shimizu, Akinori Tahara, Isao Amano, Tetsuya Nakajima
  • Patent number: 5500542
    Abstract: Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: March 19, 1996
    Assignee: Fujitsu Limited
    Inventors: Takashi Iida, Satoru Sumi, Hiroshi Shimizu, Akinori Tahara, Isao Amano, Tetsuya Nakajima
  • Patent number: 4975544
    Abstract: A connecting structure for connecting conductors used for wiring in a semiconductor device comprises a first conductor provided on a part of the semiconductor device for passing the flow of electrons, an insulator provided on the first conductor and formed with a contact hole, and a second conductor provided on the insulator for passing the flow of electrons, in which the second conductor is provided so as to sandwich the insulator together with a part of the first conductor. The first and second conductors are contacted to each other across the insulator at the contact hole so that the electrons flow through the contact hole. The contact hole extends in a general direction of a flow of electrons passing therethrough and has a stepped shape in which a width measured perpendicularly to the general direction of the flow of electrons increases stepwise towards the general direction of the flow of electrons.
    Type: Grant
    Filed: March 15, 1989
    Date of Patent: December 4, 1990
    Assignees: Fujitsu Limited, Fujitsu Vlsi Limited
    Inventors: Nobuyuki Tanaka, Taichi Saitoh, Akio Kiso, Hideo Tokuda, Tetsuya Nakajima, Minoru Takagi
  • Patent number: 4971469
    Abstract: In a printer in which a paper is pressed against a platen by a bail roller, the bail roller is automatically released from the platen, during paper loading, so as not to obstruct the paper feeding.The bail roller is pivotally moved between a loading position and a release position by a pivoting unit. The pivotal movement of the bail roller is performed by a paper feed motor so that the drive force of the paper feed motor is transmitted to the pivoting unit via a clutch unit. The connecting and disconnection of the clutch unit is controlled as a printing head carriage is moved to an outer area outside the printing area.
    Type: Grant
    Filed: January 30, 1990
    Date of Patent: November 20, 1990
    Assignee: Star Micronics Co., Ltd.
    Inventor: Tetsuya Nakajima
  • Patent number: 4747083
    Abstract: A semiconductor memory device including at least word lines and bit lines with memory cells located at each cross point therebetween. Each of the word lines is divided to form segmented word lines and each of the word line segments is driven by an individual private word driver. The individual private word drivers are activated together in response to a word selection signal. Level shifting diodes are employed in the bit line drivers to offset a voltage level change caused by the segment word drivers.
    Type: Grant
    Filed: June 28, 1984
    Date of Patent: May 24, 1988
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Nakajima, Masaki Nagahara