Patents by Inventor Tetsuya Narahara

Tetsuya Narahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6118348
    Abstract: An oscillator circuit for preventing noise from occurring in an output clock signal. The oscillator circuit contains an amplifying unit and a control signal generator. The amplifying unit contains a first amplifying circuit having a first gain and a second amplifying circuit having a second gain connected in parallel. The amplifying unit inputs an oscillating input signal and amplifies it based on an overall gain of the amplifier unit to produce an oscillating output signal. The control signal generator inputs an input control signal and generates an output control signal, and the operational state of the first amplifying circuit is switched when a value of the output control signal switches. The overall gain is based on the first gain when the first operational state of the first amplifying circuit is an enabled state and is not based on the first gain when the operational state of the first amplifying circuit is a disabled state.
    Type: Grant
    Filed: June 17, 1998
    Date of Patent: September 12, 2000
    Assignee: NEC Corporation
    Inventor: Tetsuya Narahara
  • Patent number: 5886551
    Abstract: A charge pump circuit in a phase locked loop comprises a main circuit block and an excess current cancel block for canceling a spike current. The spike current is generally supplied by a parasitic capacitance in the main circuit block and generates a jitter in the output of the phase locked loop. The excess current cancel block supplies or drains a cancel current which is substantially equal to the spike current but flows in a reverse direction.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: March 23, 1999
    Assignee: NEC Corporation
    Inventor: Tetsuya Narahara
  • Patent number: 5479044
    Abstract: A semiconductor circuit device includes a differential amplifier circuit having a first parasitic capacitor formed between the semiconductor substrate and a first resistor and a second parasitic capacitor formed between the semiconductor substrate and a second resistor. Each of the first and the second resistors is implemented by a wiring pattern over the substrate so that the first and the second parasitic capacitors are equivalent to each other.
    Type: Grant
    Filed: June 22, 1994
    Date of Patent: December 26, 1995
    Assignee: NEC Corporation
    Inventors: Tetsuya Narahara, Yasushi Matsubara
  • Patent number: 5479045
    Abstract: In a semiconductor circuit device comprising a differential amplifier circuit, which is formed on a semiconductor substrate and which comprises first and second input terminals, and a circuit element formed on the semiconductor substrate and connected to one of the first and the second input terminals. A dummy circuit element is formed on the semiconductor substrate so as to adjoin the circuit element for forming between the dummy circuit element and the semiconductor substrate a dummy parasitic capacitor which is equivalent to a parasitic capacitor formed between the circuit element and the semiconductor substrate. The dummy circuit element is connected to another one of the first and the second input terminals.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: December 26, 1995
    Assignee: NEC Corporation
    Inventors: Tetsuya Narahara, Yasushi Matsubara
  • Patent number: 5469090
    Abstract: A transistor circuit for detecting and holding a peak or bottom level of an input voltage includes a first transistor connected between a first power line and an output terminal, a capacitor connected between the output terminal and a second power line, a second transistor supplied with the input voltage and producing a current responsive to the input voltage, and a current mirror circuit supplied with the current from the second transistor as an input current and discharging the capacitor with an output current. The output current of the current mirror circuit is preferably designed to be smaller than a charging current to the capacitor from the first transistor.
    Type: Grant
    Filed: August 4, 1993
    Date of Patent: November 21, 1995
    Assignee: NEC Corporation
    Inventor: Tetsuya Narahara
  • Patent number: 5453719
    Abstract: Disclosed herein is an oscillator circuit generating an oscillation signal in response to a resonant element in a first mode and to an external clock signal in a second mode. This oscillator circuit comprises a tri-state inverter circuit and a transfer circuit between the input and output nodes of the tri-state inverter circuit, and the output node of the tri-state inverter circuit is brought into a high impedance condition when an external clock signal is used and into an active state when the resonant element is employed.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: September 26, 1995
    Assignee: NEC Corporation
    Inventor: Tetsuya Narahara
  • Patent number: 5416445
    Abstract: A clock pulse generator has a three-state inverter and a transfer gate forming in combination a feedback loop for oscillating an output clock signal in cooperation with a quartz resonator in an internal oscillation mode, and the three-state inverter enters into high-impedance state in an external oscillation mode so that an external clock signal is transferred to the output node of the three-state inverter without malfunction.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: May 16, 1995
    Assignee: NEC Corporation
    Inventor: Tetsuya Narahara
  • Patent number: 5331588
    Abstract: Out of a plurality of digit lines consisting of first layer aluminum wirings that are connected respectively to a plurality of memory cells forming a memory cell array region, and sense amplifiers that have the digit lines selected by Y selector circuits as the inputs are arranged in the direction of the digit lines of the memory cell array region. At least a part of the wirings between the plurality of the digit lines and the sense amplifiers are disposed as second layer aluminum wirings on the memory cell array region. By so arranging it is possible to provide sophisticated sense amplifiers in a semiconductor memory device which has a large number of output bits and yet a high speed operation is required for it.
    Type: Grant
    Filed: October 29, 1990
    Date of Patent: July 19, 1994
    Assignee: NEC Corporation
    Inventor: Tetsuya Narahara
  • Patent number: 5155379
    Abstract: A clocked driver circuit includes a first gate circuit, a second gate circuit, a first time constant circuit, a second time constant circuit, a first switching circuit, and a second switching circuit. The first gate circuit has one input terminal connected to a first input terminal. The second gate circuit has one input terminal connected to a second input terminal. The first time constant circuit is connected between the output terminal of the first gate circuit and the other input terminal of the second gate circuit. The second time constant circuit is connected between the output terminal of the second gate circuit and the other input terminal of the first gate circuit. The first switching circuit controls the time constant of the first time constant circuit in accordance with an output from the first gate circuit. The second switching circuit controls the time constant of the second time constant circuit in accordance with an output from the second gate circuit.
    Type: Grant
    Filed: June 13, 1991
    Date of Patent: October 13, 1992
    Assignee: NEC Corporation
    Inventor: Tetsuya Narahara