Patents by Inventor Thai Kee Gan

Thai Kee Gan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220173006
    Abstract: A chip package including a semiconductor chip is provided. The chip package may include a packaging material at least partially around the semiconductor chip with an opening extending from a top surface of the packaging material to the semiconductor chip and/or to an electrical contact structure contacting the semiconductor chip, and a thermally conductive material in the opening, wherein the thermally conductive material is configured to transfer heat from the semiconductor chip to an outside, wherein the thermally conductive material extends laterally at least partially over the top surface of the packaging material.
    Type: Application
    Filed: November 22, 2021
    Publication date: June 2, 2022
    Inventors: Thai Kee Gan, Sanjay Kumar Murugan, Ralf Otremba
  • Patent number: 11348866
    Abstract: A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: May 31, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Thai Kee Gan, Edward Fuergut, Teck Sim Lee, Lee Shuang Wang
  • Publication number: 20220139811
    Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.
    Type: Application
    Filed: November 2, 2020
    Publication date: May 5, 2022
    Inventors: Azlina Kassim, Thai Kee Gan, Mark Pavier, Ke Yan Tean, Mohd Hasrul Zulkifli
  • Publication number: 20220108949
    Abstract: One example of a semiconductor package includes a first die pad, a first die, a second die pad, and a second die. The first die pad includes a main portion and a U-shaped rail portion extending from the main portion. The first die is electrically coupled to the first die pad. The second die pad is proximate the U-shaped rail portion of the first die pad. The second die is electrically coupled to the second die pad. The second die includes a magnetic field sensor.
    Type: Application
    Filed: October 7, 2020
    Publication date: April 7, 2022
    Applicant: Infineon Technologies AG
    Inventors: Lee Shuang WANG, Thai Kee GAN, Teck Sim LEE
  • Publication number: 20220102263
    Abstract: A semiconductor package includes: a carrier having an electrically insulative body and a first contact structure at a first side of the electrically insulative body; and a semiconductor die having a first pad attached to the first contact structure of the carrier, the first pad being at source or emitter potential. The first pad is spaced inward from an edge of the semiconductor die by a first distance. The semiconductor die has an edge termination region between the edge and the first pad. The first contact structure of the carrier is spaced inward from the edge of the semiconductor die by a second distance greater than the first distance such that an electric field that emanates from the edge termination region in a direction of the carrier during normal operation of the semiconductor die does not reach the first contact structure of the carrier. Methods of production are also provided.
    Type: Application
    Filed: August 27, 2021
    Publication date: March 31, 2022
    Inventors: Chee Yang Ng, Stefan Woetzel, Edward Fuergut, Thai Kee Gan, Chee Hong Lee, Jayaganasan Narayanasamy, Ralf Otremba
  • Publication number: 20210391246
    Abstract: A lead frame includes a die pad, a row of two or more leads that extend away from a first side of the die pad, and a peripheral structure disposed opposite the die pad and connected to each lead. A first outermost lead is continuously connected to the die pad. A second outermost lead has an interior end that faces and is spaced apart from the die pad. A width of the second lead in a central span of the second lead is greater than the width of the second lead in interior and outer spans of the second lead, the interior span of the second lead separating the central span of the second lead from the interior end of the second lead, the outer span of the second lead separating the central span of the second lead from the peripheral structure.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 16, 2021
    Inventors: Thai Kee Gan, Edward Fuergut, Teck Sim Lee, Lee Shuang Wang
  • Publication number: 20210366728
    Abstract: A semiconductor package includes a die pad, a die, a first lead, a plurality of second leads, and a mold material. The die is electrically coupled to the die pad. The first lead is electrically coupled to the die. The plurality of second leads are electrically coupled to the die. The plurality of second leads are adjacent to the first lead. The mold material encapsulates at least a portion of the die pad, the die, the first lead, and the plurality of second leads. Each of the plurality of second leads extends a farther distance from the mold material than the first lead.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 25, 2021
    Applicant: Infineon Technologies AG
    Inventors: Thai Kee Gan, Edmund Sales Cabatbat
  • Patent number: 11069600
    Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Ke Yan Tean, Thomas Bemmerl, Thai Kee Gan, Azlina Kassim
  • Patent number: 11011456
    Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thai Kee Gan, Lee Shuang Wang, Jo Ean Joanna Chye
  • Publication number: 20210005541
    Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.
    Type: Application
    Filed: July 2, 2019
    Publication date: January 7, 2021
    Applicant: Infineon Technologies AG
    Inventors: Thai Kee Gan, Lee Shuang Wang, Jo Ean Joanna Chye
  • Publication number: 20200373228
    Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Ke Yan Tean, Thomas Bemmerl, Thai Kee Gan, Azlina Kassim