Patents by Inventor Thang Minh Tran

Thang Minh Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210311743
    Abstract: A microprocessor using a counter in a scoreboard is introduced to handle data dependency. The microprocessor includes a register file having a plurality of registers mapped to entries of the scoreboard. Each entry of the scoreboard has a counter that tracks the data dependency of each of the registers. The counter decrements for every clock cycle until the counter resets itself when it counts down to 0. With the implementation of the counter in the scoreboard, the instruction pipeline may be managed according to the number of clock cycles of a previous issued instruction takes to access the register which is recorded in the counter of the scoreboard.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicant: ANDES TECHNOLOGY CORPORATION
    Inventor: Thang Minh Tran
  • Publication number: 20210311741
    Abstract: A processor that includes a register file, a read shifter, a decode unit and a plurality of functional units is introduced. The register file includes a read port. The read shifter includes a plurality of shifter entries and is configured to shift out a shifter entry among the plurality of shifter entries every clock cycle. Each of the plurality of shifter entries is associated with a clock cycle and each of the plurality of shifter entries comprises a read value that indicates an availability of the read port of the register file for a read operation in the clock cycle. The decode unit is coupled to the read shifter and is configured to decode and issue an instruction based on the read values included in the plurality of shifter entries of the read shifter. The plurality of functional units is coupled to the decode unit and the register file and is configured to execute the instruction issued by the decode unit and perform the read operation to the read port of the register file.
    Type: Application
    Filed: April 7, 2020
    Publication date: October 7, 2021
    Applicant: ANDES TECHNOLOGY CORPORATION
    Inventor: Thang Minh Tran
  • Publication number: 20210303305
    Abstract: A processor that includes a register file, a latency shifter, a decode unit and a plurality of functional units is introduced. The register file includes a write port. The latency shifter includes a plurality of shifter entries and shifts out a shifter entry among the shifter entries every clock cycle. Each of the shifter entries is associated with a clock cycle and each of shifter entries includes a writeback value that indicates whether the write port of the register file is available for a writeback operation in the associated clock cycles. The decode unit is configured to decode an instruction and issue the instruction according to the writeback value of the latency shifter. The functional units are coupled to the decode unit and the register file and are configured to execute the instruction issued by the decode unit and perform writeback operation to the write port of the register file.
    Type: Application
    Filed: March 31, 2020
    Publication date: September 30, 2021
    Applicant: ANDES TECHNOLOGY CORPORATION
    Inventor: Thang Minh Tran
  • Patent number: 11132199
    Abstract: A processor that includes a register file, a latency shifter, a decode unit and a plurality of functional units is introduced. The register file includes a write port. The latency shifter includes a plurality of shifter entries and shifts out a shifter entry among the shifter entries every clock cycle. Each of the shifter entries is associated with a clock cycle and each of shifter entries includes a writeback value that indicates whether the write port of the register file is available for a writeback operation in the associated clock cycles. The decode unit is configured to decode an instruction and issue the instruction according to the writeback value of the latency shifter. The functional units are coupled to the decode unit and the register file and are configured to execute the instruction issued by the decode unit and perform writeback operation to the write port of the register file.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 28, 2021
    Assignee: ANDES TECHNOLOGY CORPORATION
    Inventor: Thang Minh Tran
  • Publication number: 20170115686
    Abstract: A digital circuitry comprising a processing unit that receives a first clock and comprising of a first self-clock circuitry that generates a first internal clock; wherein the said first self-clock circuitry further comprises of a mechanism to select between the said first clock and the first internal clock of the said processing unit for clock edge synchronization.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventor: Thang Minh Tran
  • Patent number: 8065506
    Abstract: This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: November 22, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jinwen Xi, Roman Staszewski, Thang Minh Tran
  • Publication number: 20110208950
    Abstract: A method of instruction issue (3200) in a microprocessor (1100, 1400, or 1500) with execution pipestages (E1, E2, etc.) and that executes a producer instruction Ip and issues a candidate instruction I0 (3245) having a source operand dependency on a destination operand of instruction Ip. The method includes issuing the candidate instruction I0 as a function (1720, 1950, 1958, 3235) of a pipestage EN(I0) of first need by the candidate instruction for the source operand, a pipestage EA(Ip) of first availability of the destination operand from the producer instruction, and the one execution pipestage E(Ip) currently associated with the producer instruction. A method of data forwarding (3300) in a microprocessor (1100, 1400, or 1500) having a pipeline (1640) having pipestages (E1, E2, etc.
    Type: Application
    Filed: March 21, 2011
    Publication date: August 25, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Thang Minh Tran, Raul A. Garibay, JR., James Nolan Hardage
  • Publication number: 20090063820
    Abstract: This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC architecture with addition functional blocks (ADU) tightly coupled with the based processor's data path. Each ADU accelerates a computation-intensive tasks in FDRX signal path, such as multi-tap FIRs, IIRs, complex domain and vectored data processing. The ADUs are controlled through custom instructions based on the load/store architecture. The whole FDRX data path can be easily implemented by the software employing these custom instructions.
    Type: Application
    Filed: August 18, 2008
    Publication date: March 5, 2009
    Inventors: Jinwen Xi, Roman Staszewski, Thang Minh Tran
  • Patent number: 7475231
    Abstract: A system and a method to identify a conditional branch instruction having a program counter and a target address, and increment a loop count each time the program counter and the target address equal a stored program counter and a target address. The system and method additionally includes assignment of a start loop pointer and an end loop pointer, based on an offset, when the loop count is equal to a threshold value, and capturing instructions for a loop, as defined by the start loop pointer and the end loop pointer, in an instruction queue.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: January 6, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Thang Minh Tran
  • Patent number: 6065126
    Abstract: A self-timed and self-enabled distributed clock is provided for a functional unit that has variable executing time. The self-timed clock provides plurality of clock pulses within a clock cycle for latching of result and starting execution of the next operation. The functional unit can execute more than one operation per clock cycle thus increasing the utilization of the execute unit and the performance of the processor. The state machine is designed to keep track of the current clock pulse and the execution time of the current operation. The functional unit includes the output queue buffer to keep plurality of results from execute unit. The functional unit executes data close to its optimal timing while the data between functional units are synchronized on the clock boundary as in synchronous design. It is more efficient than synchronous design yet the outputs are deterministic as the clocking is preserved in the design.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: May 16, 2000
    Inventors: Thang Minh Tran, Rupaka Mahalingaiah
  • Patent number: 6005793
    Abstract: A cache memory consists of plurality of memory bits within a random-access memory (RAM) cell. An extra address decode circuit is needed to select a single memory bit within the multi-bit RAM cell before normal access of RAM array circuit. Combining of multiple bits into a RAM cell reduces the number of interconnections in comparison to single bit RAM cell. This technique eliminates the need to break up the cache array into multiple sets for reducing power dissipation. The area advantages are also from optimal layout of multi-bit RAM cell, address decoder, and sense amplifier unit. Furthermore, the interconnections can be widened to reduce the RC delay as it is a dominating factor in future technology advancement. The multiplexing of the bits are done before the row decoding thus reducing one level of multiplexing after reading of data from the sense amplifier units.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: December 21, 1999
    Inventor: Thang Minh Tran