Patents by Inventor Thanunathan Rangarajan

Thanunathan Rangarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10732854
    Abstract: A data processing system and a method of runtime configuration of the data processing system are disclosed. The data processing system comprises a plurality of home nodes, and for a data store associated with a slave node in the data processing system, for each home node of the plurality of home nodes a modified size of the data store is determined. The modified size is based on a storage capacity of the data store and at least one additional property of the data processing system. A chosen home node of the plurality of home nodes is selected which satisfies a minimization criterion for the modified size, and the chosen home node is paired with the slave node.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: Bruce James Mathewson, Carlos Garcia-Tobin, Phanindra Kumar Mannava, Thanunathan Rangarajan
  • Patent number: 10705561
    Abstract: A method for configuring a clock distribution system for an integrated circuit involves receiving an indication of frequencies of clock signal to supply to devices on the integrated circuit, selecting a configuration for the clock distribution system based on the frequencies required by the devices and an estimated power consumption, and providing an indication of the selected configuration for configuring the clock distribution system.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: July 7, 2020
    Assignee: Arm Limited
    Inventors: Thanunathan Rangarajan, Ronald Cron, Sudeep Karkada Nagesha Holla
  • Patent number: 10565039
    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventor: Thanunathan Rangarajan
  • Publication number: 20190347011
    Abstract: A data processing system and a method of runtime configuration of the data processing system are disclosed, the data processing system comprising a plurality of home nodes, and the method comprising, for a data store associated with a slave node in the data processing system, determining for each home node of the plurality of home nodes a modified size of the data store, the modified size being based on a storage capacity of the data store and at least one additional property of the data processing system. The method also comprises selecting a chosen home node of the plurality of home nodes which satisfies a minimization criterion for the modified size, and pairing the chosen home node with the slave node.
    Type: Application
    Filed: May 11, 2018
    Publication date: November 14, 2019
    Inventors: Bruce James MATHEWSON, Carlos GARCIA-TOBIN, Phanindra Kumar MANNAVA, Thanunathan RANGARAJAN
  • Patent number: 10306420
    Abstract: Embodiments of self-locating computing devices, systems, and methods are described. In some embodiments, a computing device may include a Wireless Credential Exchange Module (WCEM) to detect one or more location tags and a management engine, coupled to the WCEM, to retrieve information of the one or more location tags from the WCEM, and to provide an asset management server with an identifier of the computing device and the information of the one or more location tags or location information of the computing device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Shen Zhou, Zhijie Sheng, Thanunathan Rangarajan, Junjie Huang
  • Publication number: 20190138378
    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Applicant: Intel Corporation
    Inventor: Thanunathan Rangarajan
  • Publication number: 20190138379
    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Applicant: Intel Corporation
    Inventor: Thanunathan Rangarajan
  • Publication number: 20190129777
    Abstract: Method, system, and apparatus for predicting imminent memory failures based on one or more adverse conditions being subjected to the memory. One embodiment of a method comprises: tracking one or more corrected memory errors (CEs) in a memory; tracking one or more generated tokens, wherein the tokens are being generated at an initial rate; detecting one or more adverse conditions being subjected to the memory and responsive to the detection, reduce the rate at which the tokens are being generated; decrementing the tracked CEs based on a reoccurring leak timer, wherein upon each expiration of the reoccurring leak timer, the tracked CEs is decremented by one so long as there is at least one tracked token; reducing the tracked tokens by one in response to the decrement of the tracked CEs; and triggering a CE overflow signal upon detecting a count of the tracked CEs exceeding an overflow limit.
    Type: Application
    Filed: February 16, 2017
    Publication date: May 2, 2019
    Inventor: Thanunathan Rangarajan
  • Publication number: 20190108080
    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.
    Type: Application
    Filed: July 16, 2018
    Publication date: April 11, 2019
    Inventor: Thanunathan Rangarajan
  • Patent number: 10169268
    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
  • Patent number: 10025647
    Abstract: A method and system for storing hints in poisoned data of a computer system memory includes receiving poisoned data in a component of the system; forwarding the poisoned data to a memory controller of the system; and forwarding additional data regarding the poisoned data to a memory controller. The memory controller writes the poisoned data to the system memory wherein the written poisoned data includes a poison signature and a hint based on the additional data regarding the poisoned data; and when the written poisoned data is read signaling a system error and returning the poison signature and the hint to a system software of the system.
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventor: Thanunathan Rangarajan
  • Patent number: 9990016
    Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 5, 2018
    Assignee: Intel Corporation
    Inventors: Thanunathan Rangarajan, Vinayak P. Risbud, Tabassum Yasmin
  • Publication number: 20180143923
    Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
    Type: Application
    Filed: January 17, 2018
    Publication date: May 24, 2018
    Inventors: Mahesh Natu, Thanunathan Rangarajan, Gautam Doshi, Shamanna M. Datta, Baskaran Ganesan, Mohan J. Kumar, Rajesh S. Parthasarathy, Frank Binns, Rajesh Nagaraja Murthy, Robert C. Swanson
  • Publication number: 20180077537
    Abstract: Embodiments of self-locating computing devices, systems, and methods are described. In some embodiments, a computing device may include a Wireless Credential Exchange Module (WCEM) to detect one or more location tags and a management engine, coupled to the WCEM, to retrieve information of the one or more location tags from the WCEM, and to provide an asset management server with an identifier of the computing device and the information of the one or more location tags or location information of the computing device. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 3, 2015
    Publication date: March 15, 2018
    Inventors: Shen ZHOU, Zhijie SHENG, Thanunathan RANGARAJAN, Junjie HUANG
  • Patent number: 9857809
    Abstract: In an embodiment, a processor includes a fuzzy thermoelectric cooling (TEC) controller to: obtain a current TEC level associated with the processor; obtain a current fan power level associated with the processor; fuzzify the current TEC level to obtain a first fuzzy fan level; fuzzify the current fan power level to obtain a second fuzzy fan level; determine a new TEC power level based at least in part on the first fuzzy fan level, the second fuzzy fan level, and a plurality of fuzzy rules; and provide the new TEC power level to a TEC device associated with the processor, where the TEC device is to transfer heat from the processor to a heat sink. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Thanunathan Rangarajan, Rahul Khanna, Rafael De La Guardia Gonzalez, Minh T. Le
  • Patent number: 9852299
    Abstract: The present disclosure is directed to a protection scheme for remotely-stored data. A system may comprise, for example, at least one device including at least one virtual machine (VM) and a trusted execution environment (TEE). The TEE may include an encryption service to encrypt or decrypt data received from the at least one VM. In one embodiment, the at least one VM may include an encryption agent to interact with interfaces in the encryption service. For example, the encryption agent may register with the encryption service, at which time an encryption key corresponding to the at least one VM may be generated. After verifying the registration of the encryption agent, the encryption service may utilize the encryption key corresponding to the at least one VM to encrypt or decrypt data received from the encryption agent. The encryption service may then return the encrypted or decrypted data to the encryption agent.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 26, 2017
    Assignee: INTEL CORPORATION
    Inventors: Hariprasad Nellitheertha, Deepak S., Thanunathan Rangarajan, Anil S. Keshavamurthy
  • Publication number: 20170351308
    Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.
    Type: Application
    Filed: August 11, 2017
    Publication date: December 7, 2017
    Inventors: Thanunathan Rangarajan, Vinayak P. Risbud, Tabassum Yasmin
  • Patent number: 9817054
    Abstract: Methods and apparatus relating to electrical margining of multi-parameter high-speed interconnect links with multi-sample probing are described. In one embodiment, logic is provided to generate one or more parameter values, corresponding to an electrical operating margin of an interconnect. The one or more parameter values are generated based on a plurality of eye observation sets to be detected in response to operation of the interconnect in accordance with a plurality of parameter sets (e.g., by using quantitative optimization techniques). In turn, the interconnect is to be operated at the one or more parameter values if it is determined that the one or more parameter values cause the interconnect to operate at an optimum level relative to an operation of the interconnect in accordance with one or more less optimum parameter levels. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: November 14, 2017
    Assignee: Intel Corporation
    Inventors: Thanunathan Rangarajan, Shreesh Chhabbi, Arvind A. Kumar, Venkatraman Iyer
  • Patent number: 9760136
    Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: September 12, 2017
    Assignee: Intel Corporation
    Inventors: Thanunathan Rangarajan, Vinayak P. Risbud, Tabassum Yasmin
  • Patent number: 9684457
    Abstract: Provided are a computer readable storage media, method, and system for gathering sensed data from devices to manage host command transmission and cooling of the device. Host commands are retrieved from a host memory in a host to perform Input/Output operations with respect to a device. The retrieved host commands are transmitted to the device to perform the I/O operations of the host command. A monitor command is transmitted to obtain sensed data from the device while processing the host commands. A rate of transmitting the host commands is adjusted in response to determining that the sensed data received from the device in response to the monitor command satisfies a condition.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: June 20, 2017
    Assignee: INTEL CORPORATION
    Inventors: Thanunathan Rangarajan, Eng Hun Ooi, Madhusudhan Rangarajan, Robert W. Cone, Nishi Ahuja