Patents by Inventor Theo J. Powell

Theo J. Powell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7328388
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: February 5, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Patent number: 7278078
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: October 2, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Patent number: 6801461
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: October 5, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Publication number: 20020089887
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Application
    Filed: December 17, 2001
    Publication date: July 11, 2002
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Publication number: 20020071325
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Application
    Filed: August 28, 2001
    Publication date: June 13, 2002
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Patent number: 6353563
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: March 5, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Patent number: 6014336
    Abstract: A test enable control for a built-in self-test of a memory device is provided. In one embodiment of the present invention, a test enabling system is provided. The test enabling system comprises an enable test circuit (62), a plurality of test algorithms stored in a read only memory (72) and a program counter (66) operable to control the execution of the test algorithm. The first instruction of each test is a jump test enable instruction (130) comprising a jump test instruction and an address in the read only memory (72) corresponding to the next test algorithm. The enable test circuit (62) is operable to signal to the program counter (66) if a particular test algorithm is enabled.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: January 11, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, Kuong Hua Hii, Danny R. Cline
  • Patent number: 5959912
    Abstract: A read-only memory (ROM) embedded mask release number for a built-in self-test of a memory device is provided. A synchronous dynamic random access memory (10) comprises a conventional memory (12) and a built-in self-test arrangement (14). The built-in self-test arrangement (14) includes a read only memory (ROM) (72) which stores a plurality of algorithms. Each algorithm is comprised of a series of array access instructions (140) and program access instructions (142). The last instruction in ROM (72) is an idle instruction (120). Associated with idle instruction (120) is an identification number (132). Once stored in ROM (72), the identification number (132) can be read without the use of additional equipment.
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: September 28, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, Kuong Hua Hii, Danny R. Cline, Wah Kit Loh
  • Patent number: 5953272
    Abstract: A data invert jump instruction test for a built-in self-test of a memory device is provided. The data invert system comprises a read only memory (72) operable to store a plurality of test algorithms wherein at least one of the test algorithms includes a data invert jump instruction (160). Also included is a data invert circuit (178) coupled to the read only memory (72) and a toggle register (188) within the data invert circuit (178). The toggle register (188) is set to one when the data invert jump instruction (160) occurs for the first time in the test algorithm. This causes the data invert circuit (178) to output the inverse of the data inputted through the data invert circuit (178).
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: September 14, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, Kuong Hua Hii, Danny R. Cline
  • Patent number: 5936900
    Abstract: An integrated circuit memory device (10) is provided that has a self test monitor mode. The memory device (10) includes a memory array (26) having a plurality of memory cells. The memory device (10) further includes a built-in self test circuit (12) connected to receive a self test select signal. The built-in self test circuit (12) is operable, when the memory device (10) is in self test mode, to generate internal self test signals for operating and testing the memory array (26). A data buffer (28) is connected to receive the internal self test signals and a monitor mode signal. The data buffer (28) is operable, when the memory device (10) is in self test monitor mode, to connect the internal self test signals to terminals of the memory device (10) to provide the internal self test signals externally from the memory device (10). The monitored internal self test signals can be used to verify operation of the built-in self test circuit (12).
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: August 10, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Theo J. Powell, Daniel R. Cline
  • Patent number: 5923599
    Abstract: In a built-in-self-test (BIST) unit or a memory unit, an address limits unit is provided which, prior to initiation of the test procedures, has start and stop addresses stored therein. Upon the initiation of the test procedures by the BIST unit, the start address of the address limits unit is transferred to the address counters units wherein the start address serves as the initial test address. The stop address is transferred to the address counters unit wherein the stop address will be compared with the current address. When the stop address and the current address match, the test procedure being executed by the BIST unit will be terminated. In this manner, any subarray in the memory unit can be selected for test.
    Type: Grant
    Filed: April 29, 1997
    Date of Patent: July 13, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong H. Hii, Danny R. Cline, Theo J. Powell, Wah K. Loh
  • Patent number: 5883843
    Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: March 16, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Danny R. Cline, Theo J. Powell
  • Patent number: 5875153
    Abstract: An internal/external clock option for built in self test is provided. In one embodiment of the present invention, a clock selection circuit (150) is provided. The clock selection circuit (150) comprises an external clock source (152) and an internal clock source (177). A first multiplexer (164) is provided and has the external clock source (152) and the internal clock source (177) as data inputs and an internal clock selection bit value (B.sub.-- CLKMUXB 176) as a data select input. A second multiplexer (156) having the external clock (152) and the output of the first multiplexer as data inputs and a data select input (BCLK.sub.-- EN) based on whether a self-test mode is activated (BIST.sub.-- EN) and the internal clock selection bit value (B.sub.-- CLKMUXB) is also provided. The external clock source (152) or internal clock source (177) is selected based on the value of the internal clock selection bit value (B.sub.-- CLKMUXB 176) and whether the self test mode is activated (BIST.sub.-- EN).
    Type: Grant
    Filed: January 9, 1998
    Date of Patent: February 23, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Kuong Hua Hii, Theo J. Powell, Danny R. Cline
  • Patent number: 5694402
    Abstract: A system (13) is provided for structurally testing an integrated circuit device, The system includes a signature analyzer (14) operable to compress test results received from the integrated circuit device into a signature. A control device (20) is coupled to the signature analyzer (14), The control device (20) is operable to enable the compression operation of the signature analyzer (14) when the test results contain known states and disable the compression operation when the test results contain unknown states.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: December 2, 1997
    Assignee: Texas Instruments Incorporated
    Inventors: Kenneth M. Butler, Theo J. Powell
  • Patent number: 5032783
    Abstract: A test circuit for a logic device having ports. The test circuit includes a serial scan path for serially transferring externally generated test vectors from a serial test input to a serial test output. A storing circuit stores a data bit and has a node at which the data bit is stored. A first interface circuit interfaces the node with a first one of the ports for synchronous transfer of data from the logic device to the node. A second interface circuit interfaces the node with the serial scan path to tranbsfer data from the serial scan path to the node. A coupling circuit connects the storing circuit to a second of the ports to transfer a logic level responsive to the data bit to the logic device during test. Also the coupling circuit temporarily couples the data bit from the node to the serial scan path also during test.
    Type: Grant
    Filed: July 10, 1989
    Date of Patent: July 16, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Yin-Chao Hwang, Theo J. Powell
  • Patent number: 5012471
    Abstract: An automatic test pattern generator and process assigns value-strength number to selected nodes representing the electrical characteristic strength of integrated circuits including field effect transistors and the logic state values at those nodes. These value-strength numbers become sensitized to the inputs of the selected node and become propagated to outputs of the selected node for establishing patterns for test signals. The test signals later become used in chip testers for determining good and bad integrated circuit chips. The value-strength numbers also become used in dynamic testing of the integrated circuit nodes by using clock signals of the integrated circuit to establish a transition at a start node of a test path. Within a known clock period later, the transition should become captured at an end node of the test path.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: April 30, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, John I. Hickman, Jeri J. Crowley
  • Patent number: 4870346
    Abstract: Simple polynomial function generators are used to generate pseudo random test patterns and perform signature analysis on a per pin basis in the control logic in LSI/VLSI test systems.
    Type: Grant
    Filed: September 14, 1987
    Date of Patent: September 26, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Marc R. Mydill, Theo J. Powell
  • Patent number: 4710933
    Abstract: A testable logic circuit includes parallel registers (72)-(80) for interfacing with a common internal bus (70). The parallel registers (72)-(80) are individually addressable by an address decoder (104) for storage of test vectors therein. These test vectors are then applied to associated logic circuits. Individual shift register latches (92)-(102) are provided at imbedded locations therein. The shift register latches are interfaced with a serial data link to allow serial loading of data therein. The parallel latches function in both the test mode to store test vectors for application to the associated logic and also in the operational mode for storage of logic data. Use of parallel registers increases the speed at which data is scanned into the device.
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: December 1, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, Jeffrey D. Bellay, Martin D. Daniels, Yin-Chao Hwang
  • Patent number: 4710931
    Abstract: A test partitionable logic circuit comprises a plurality of functional modules (26a)-(26n). Each of the functional modules is interfaced with the exterior of the logic circuit with a data bus (20), address bus (16) and a control bus (12). Each of the modules (26) is addressable through an address decode/select circuit (52) to operationally isolate the select modules and define a test boundary. Test data is scanned into a serial chain of shift register latches (SRL's) which are connected in a daisy chain configuration. The defined test boundary allows each of the modules to be separately selected and tested such that the test program for an individual module is separate and distinct.
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: December 1, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey D. Bellay, Theo J. Powell
  • Patent number: 4701921
    Abstract: A modularized scanned logic test system includes modularized logic circuits (26) having control/observation locations therein. Each of the control/observation locations has a shift register latch (SRL) disposed thereat. A common scan data in line (28) provides data to a serial input to each of the modules (26). The serial output of each of the modules (26) is interfaced with a scan data out line (30). An address on a bus (16) is provided to a decoder (52) to select one of the modules (26). An isolation gate (48) allows for input of data to only the select one of the modules (26) and an isolation gate (50) allows output of data only from the select one of the modules (26) to the scan data out line (30).
    Type: Grant
    Filed: October 23, 1985
    Date of Patent: October 20, 1987
    Assignee: Texas Instruments Incorporated
    Inventors: Theo J. Powell, Yin-Chao Hwang