Patents by Inventor Theresa Kramer Guarini

Theresa Kramer Guarini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220301920
    Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and to apparatus for use within a substrate processing chamber to improve film thickness uniformity. More specifically, the embodiments of the disclosure relate to an edge ring. The edge ring may include an overhang ring.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Kin Pong LO, Vladimir NAGORNY, Wei LIU, Theresa Kramer GUARINI, Bernard L. HWANG, Malcolm J. BEVAN, Jacob ABRAHAM, Swayambhu Prasad BEHERA
  • Patent number: 11450759
    Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: September 20, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Steven C. H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
  • Patent number: 11380575
    Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and to apparatus for use within a substrate processing chamber to improve film thickness uniformity. More specifically, the embodiments of the disclosure relate to an edge ring. The edge ring may include an overhang ring.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 5, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Kin Pong Lo, Vladimir Nagorny, Wei Liu, Theresa Kramer Guarini, Bernard L. Hwang, Malcolm J. Bevan, Jacob Abraham, Swayambhu Prasad Behera
  • Publication number: 20220178747
    Abstract: One or more embodiments described herein generally relate to systems and methods for calibrating an optical emission spectrometer (OES) used for processing semiconductor substrates. In embodiments herein, a light fixture is mounted to a plate within a process chamber. A light source is positioned within the light fixture such that it provides an optical path that projects directly at a window through which the OES looks into the process chamber for its reading. When the light source is on, the OES measures the optical intensity of radiation from the light source. To calibrate the OES, the optical intensity of the light source is compared at two separate times when the light source is on. If the optical intensity of radiation at the first time is different than the optical intensity of radiation at the second time, the OES is modified.
    Type: Application
    Filed: March 27, 2020
    Publication date: June 9, 2022
    Inventors: Kin Pong LO, Lara HAWRYLCHAK, Malcolm J. BEVAN, Theresa Kramer GUARINI, Wei LIU, Bernard L. HWANG
  • Publication number: 20220028656
    Abstract: Embodiments of the present disclosure generally relate to the fabrication of integrated circuits and to apparatus for use within a substrate processing chamber to improve film thickness uniformity. More specifically, the embodiments of the disclosure relate to an edge ring. The edge ring may include an overhang ring.
    Type: Application
    Filed: July 27, 2020
    Publication date: January 27, 2022
    Inventors: Kin Pong LO, Vladimir NAGORNY, Wei LIU, Theresa Kramer GUARINI, Bernard L. HWANG, Malcolm J. BEVAN, Jacob ABRAHAM, Swayambhu Prasad BEHERA
  • Patent number: 11145761
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood, Nam Sung Kim
  • Publication number: 20210104617
    Abstract: Described is a method of manufacturing a gate-all-around electronic device. The method includes forming a thermal oxide layer though an enhanced in situ steam generation process in combination with atomic layer deposition of a low-? layer. The thin thermal oxide layer passivates the interface between the silicon layer and the dielectric layer of the GAA. A passivation process after the deposition of the low-? layer reduces the bulk trap and enhances the breakdown performance of the GAA transistor.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 8, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Steven C.H. Hung, Benjamin Colombeau, Andy Lo, Byeong Chan Lee, Johanes F. Swenberg, Theresa Kramer Guarini, Malcolm J. Bevan
  • Patent number: 10971357
    Abstract: A method of modifying a layer in a semiconductor device is provided. The method includes depositing a low quality film on a semiconductor substrate, and exposing a surface of the low quality film to a first process gas comprising helium while the substrate is heated to a first temperature, and exposing a surface of the low quality film to a second process gas comprising oxygen gas while the substrate is heated to a second temperature that is different than the first temperature. The electrical properties of the film are improved by undergoing the aforementioned processes.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: April 6, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Wei Liu, Theresa Kramer Guarini, Linlin Wang, Malcolm Bevan, Johanes S. Swenberg, Vladimir Nagorny, Bernard L. Hwang, Kin Pong Lo, Lara Hawrylchak, Rene George
  • Publication number: 20210043448
    Abstract: Processing platforms having a central transfer station with a robot and an environment having greater than or equal to about 0.1% by weight water vapor, a pre-clean chamber connected to a side of the transfer station and a batch processing chamber connected to a side of the transfer station. The processing platform configured to pre-clean a substrate to remove native oxides from a first surface, form a blocking layer using a alkylsilane and selectively deposit a film. Methods of using the processing platforms and processing a plurality of wafers are also described.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 11, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Ning Li, Mihaela A. Balseanu, Li-Qun Xia, Dongqing Yang, Lala Zhu, Malcolm J. Bevan, Theresa Kramer Guarini, Wenbo Yan
  • Publication number: 20210010160
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Christopher S. OLSEN, Theresa Kramer GUARINI, Jeffrey A. TOBIN, Lara HAWRYLCHAK, Peter STONE, Chi Wei LO, Saurabh CHOPRA
  • Publication number: 20200161171
    Abstract: Generally, examples described herein relate to methods and processing systems for forming isolation structures (e.g., shallow trench isolations (STIs)) between fins on a substrate. In an example, fins are formed on a substrate. A liner layer is conformally formed on and between the fins. Forming the liner layer includes conformally depositing a pre-liner layer on and between the fins, and densifying, using a plasma treatment, the pre-liner layer to form the liner layer. A dielectric material is formed on the liner layer.
    Type: Application
    Filed: September 23, 2019
    Publication date: May 21, 2020
    Inventors: Benjamin COLOMBEAU, Theresa Kramer GUARINI, Malcolm BEVAN, Rui CHENG
  • Publication number: 20200111659
    Abstract: A method of modifying a layer in a semiconductor device is provided. The method includes depositing a low quality film on a semiconductor substrate, and exposing a surface of the low quality film to a first process gas comprising helium while the substrate is heated to a first temperature, and exposing a surface of the low quality film to a second process gas comprising oxygen gas while the substrate is heated to a second temperature that is different than the first temperature. The electrical properties of the film are improved by undergoing the aforementioned processes.
    Type: Application
    Filed: October 4, 2018
    Publication date: April 9, 2020
    Inventors: Wei LIU, Theresa Kramer GUARINI, Linlin WANG, Malcolm BEVAN, Johanes S. SWENBERG, Vladimir NAGORNY, Bernard L. HWANG, Kin Pong LO, Lara HAWRYLCHAK, Rene GEORGE
  • Patent number: 10573719
    Abstract: Embodiments described herein generally relate to methods and apparatus for horizontal gate all around (hGAA) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. The different materials may be silicon containing materials and one or more III/V materials. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: February 25, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Benjamin Colombeau, Michael Chudzik
  • Publication number: 20200035822
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi WOOD, Nam Sung KIM
  • Publication number: 20190385825
    Abstract: Embodiments described herein generally relate to a method and apparatus for fabricating a chamber component for a plasma process chamber. In one embodiment a chamber component used within a plasma processing chamber is provided that includes a metallic base material comprising a roughened non-planar first surface, wherein the roughened non-planar surface has an Ra surface roughness of between 4 micro-inches and 80 micro-inches, a planar silica coating formed over the roughened non-planar surface, wherein the planar silica coating has a surface that has an Ra surface roughness that is less than the Ra surface roughness of the roughened non-planar surface, a thickness between about 0.2 microns and about 10 microns, less than 1% porosity by volume, and contains less than 2E12 atoms/centimeters2 of aluminum.
    Type: Application
    Filed: May 21, 2019
    Publication date: December 19, 2019
    Inventors: Jian WU, Wei LIU, Theresa Kramer GUARINI, Linlin WANG, Malcolm BEVAN, Lara HAWRYLCHAK
  • Patent number: 10490666
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 26, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Shiyu Sun, Nam Sung Kim, Naomi Yoshida, Theresa Kramer Guarini, Sung Won Jun, Vanessa Pena, Errol Antonio C. Sanchez, Benjamin Colombeau, Michael Chudzik, Bingxi Wood
  • Patent number: 10290504
    Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: May 14, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Theresa Kramer Guarini, Huy Q. Nguyen, Malcolm Bevan, Houda Graoui, Philip A. Bottini, Bernard L. Hwang, Lara Hawrylchak, Rene George
  • Publication number: 20180211833
    Abstract: Processing platforms having a central transfer station with a robot and an environment having greater than or equal to about 0.1% by weight water vapor, a pre-clean chamber connected to a side of the transfer station and a batch processing chamber connected to a side of the transfer station. The processing platform configured to pre-clean a substrate to remove native oxides from a first surface, form a blocking layer using a alkylsilane and selectively deposit a film. Methods of using the processing platforms and processing a plurality of wafers are also described.
    Type: Application
    Filed: January 24, 2018
    Publication date: July 26, 2018
    Inventors: Ning Li, Mihaela Balseanu, Li-Qun Xia, Dongqing Yang, Lala Zhu, Malcolm J. Bevan, Theresa Kramer Guarini, Wenbo Yan
  • Publication number: 20180082847
    Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.
    Type: Application
    Filed: November 27, 2017
    Publication date: March 22, 2018
    Inventors: Wei LIU, Theresa Kramer GUARINI, Huy Q. NGUYEN, Malcolm BEVAN, Houda GRAOUI, Philip A. BOTTINI, Bernard L. HWANG, Lara HAWRYLCHAK, Rene GEORGE
  • Publication number: 20180061978
    Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Inventors: Shiyu SUN, Naomi YOSHIDA, Theresa Kramer GUARINI, Sung Won JUN, Vanessa PENA, Errol Antonio C. SANCHEZ, Benjamin COLOMBEAU, Michael CHUDZIK, Bingxi Sun WOOD, Nam Sung KIM